Newbie Question: Using Includes in Verilog

This is a very basic question. I would appreciate your help. I have a Xilinx FPGA Verilog project that containts several files. I would like to use an include file for some definitions that I would like to use in several files.

I addeded the line:

`include "definitions.v"

to one of the .v modules containing the FPGA code.

definitions.h contains the following:

//definitions.h

parameter NO_SELECT = 16'h00, REG1_ADDRESS = 16'h01, REG2_ADDRESS = 16'h02, REG3_ADDRESS = 16'h03, REG4_ADDRESS = 16'h04, REG5_ADDRESS = 16'h05, BLOCK1_ADDRESS = 16'h06, REG1_SELECT = 16'h01, REG2_SELECT = 16'h02, REG3_SELECT = 16'h04, REG4_SELECT = 16'h08, REG5_SELECT = 16'h10, BLOCK1_SELECT = 16'h20;

From Xilinx ISE I get the following error:

ERROR:HDLCompilers:26 - "rtl/definitions.v" line 2 expecting 'EOF', found 'parameter'

When I compile in ModelSim I get the following error:

What am i doing wrong? How to get ModelSim to find the include file (it is in the same directory as the Verilog modules)?

Thanks for your help.