Convert Schematic Files (.sch) to Verilog Files (.v) for simulation in ModelSim

Craig,

Depending on what tools you used to capture the schematic, and what models your flow supports, asking for a "verilog netlist" is a feature of some tools.

The resulting verilog netlist will be at the transistor and wire level, or gate level (which in the hierarchy is made up of gates and wires), and will basically allow you to functionally simulate the schematic, less any timing, or 'analog' behavior (after all, you only have 1's,

0's, 'don't cares', tri-states, and unknowns).

This is commonly done for ASIC/ASSP design: one may synthesize higher level RTL (like verilog and VHDL descriptions that have no specific technology or functional modules like 'multiply this by that') into lower level schematics of transistors (from standard cell library gates).

The resulting circuit netlist (like a spice netlist) will allow one to perform many good (analog) simulations, but will either take too long, or blow up, if there are close to a billion devices in the chip. The next choice is to simulate the verilog netlist of the wires and transistors, which will run much much faster, but will be unable to tell you anything about time, voltage, or current.

Since you posted on c.a.f. I am going to presume your HDL was synthesized for a FPGA, and then it was placed, and routed in the FPGA.

You may also have a schematic of how the HDL blocks are connected together. The resultant netlist is in some format (for Xilinx: XDL) which may then be simulated quickly for the functional behavior.

In an FPGA, the translation all the way down to transistors is not provided, like it would be in the ASIC/ASSP flow....

Make sense?

Austin

Austin,

How accurate is the timing for post place and route simulations using the Xilinx libraries?

---Matthew Hicks

Matthew,

We stand by the speeds files. In other words, if the actual part is slower, on any path or feature, it may be returned (via the RMA process), and we issue a new one that meets the specifications.

I have taken part in many such cases, and on only two occasions, we had made a mistake in the speeds file, and we had to offer a faster speed grade part to the customer, or work with them to improve their timing to get around the failing path.

It is so extremely painful to have to issue a new (slower) speeds file for our customers; we only do that when we have no other alternative whatsoever (and you can believe we get hammered internally for having the wrong number in the speeds file).

The same is true for IBIS models, packaging files, etc.

Austin

Sorry I'm trying to be very practical here. I just want to know what command line tools I can use to create a verilog file from a schematic file.

How do I do that from the command line using either ISE 9.1i or ModelSim?

I'd appreciate it if you could give me an example?

Lets say my schematic is named: circuit.sch

I'd like to create a verilog file (netlist) that is equivilent to it, say: circuit.v

I'm guessing at the command line it would be something like:

xst -sch circuit.sch > circuit.v

I have read through all the user manuals, developer manuals, etc... I can't not figure out how to do this outside of the GUI interface.

Thanks again for any help you can provide.

Thanks, Craig.

Hi Craig, it's so simple:

sch2verilog

is the name of the program. and this is how to use it :

Release 9.1.01i - sch2verilog J.31 Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. Usage: sch2verilog [-intstyle ] [-top] [-tf] [-tfonly] [-tfext ] [-ti] [-tionly] [-tiext ] [-nodrc] [-nets] [-NETS] [-inst] [-INST] [-MODEL] [-model] [-iterated] [-family ] [-synthesis ] [-w]

[] -intstyle Indicate contextual information when invoking Xilinx applications within a flow or project environment. can be ise, xflow or silent -top Write out the top-level schematic only -tf Generate test fixture file -tfonly Generate test fixture file only -tfext Set test fixture file extension (Default: vf) -ti Generate instantiation template file -tionly Generate instantiation template file only -tiext Set instantiation template file extension (Default: vi) -nodrc Disable DRC check -NETS Force net and pin names to uppercase -nets Force net and pin names to lowercase -INST Force instance names to uppercase -inst Force instance names to lowercase -MODEL Force VeriModel names to uppercase -model Force VeriModel names to lowercase -iterated Don't Use underscores when expanding iterated names -family Specify device family (Default: virtex) -synthesis Specify synthesis tool: XST, EXEMPLAR, PRECISION, SYNPLICITY (Default: XST) -w Overwrite existing file without warning Input file name (Default extension: .sch) Output file name (Default: .v)

So all you need for your everyday work is:

sch2verilog -family virtex_or_whatever_U_use circuit.sch circuit.vf

For your modelsim question: Yes: if you split your script in two parts: a shell script that converts the schematics (and does the compilation of your sources if you like) and the modelsim do script that controls your simulation. Remember: vlib vmap and vlog (vcom for vhdl users) are independent programs that can run without a modelsim gui. depending on your scripting skills you can even prevent the simulator to start before the sources are all compiled successfully.

e.g.:

#! /bin/sh # if you are a unix user sch2verilog -family circuit_1.sch circuit_1.vf #...many more sch2verilog -family circuit_n.sch circuit_n.vf vlib yourlib vmap yourlib yourlib_path vlog [options] circuit_1.vf #...many more vlog [options] circuit_n.vf vsim -do sim_script.do # end of sh script

#sim_script vlog [options] testbench.v

vsim [options] testbench view wave -undock do wave_circuit.do # or add wave *

run -all # end of sim_script

Craig,

I must apologize, because I am an IC designer, not really a FPGA user (I mostly use very simple and straightforward designs to verify the blocks, and rely on others to write the systems level stuff).

I am also not a software expert.

There are Xilinx employees who read this newsgroup from our software group, however.

If they do not respond, I am going to have to assume we can not do what you ask with our tools.

Aust> Sorry I'm trying to be very practical here. I just want to know what

Usually most command issued by the ISE GUI are appended to a file /.cmd_log

if You cleanup all project files and "rebuild all" You can have in that file all the command line to issue to rebuild your project (NOTE ofter the rebuild You souldn't re-cleanup the project files else you lose something...and the command line couldn't work...)

I don't know if that is the case for "sch2verilog" too... let try !

Sandro

HI Craig,

As Eilert pointed out, you can use sch2verilog and sch2vhdl to convert the schematic file that comes from ECS. This is the biggest confusion I am hearing. ECS is the schematic capture tool you probably have never heard this name used before. XST does not write out schematics. XST is the Xilinx Synthesis tool. Basically what happens in the back end is for us to convert it to HDL and then run XST on it.

Regarding your question on whether you can mix schematic and HDL in modelsim, the answer is no. Modelsim is a HDL simulator only. It cannot simulate gates. This is why you can psuedo implement this by the method that Eilert provided that is to write a tcl script that runs sch2verilog and then runs the simulation. You can combine the shell script and do file into one Tcl file if you use the exec command.

Thanks Duth

Eilert,

Thanks very much for your detailed response that is exactly what I needed. I have written a bash script that automatically verifies the functionality of a series of test circuits that use a specific module I've developed. I was trying to come up with a way to quickly verify that I haven't violated any rules with change I've made to that module. However, I have a college that developed part of his work in schematic, and I was having to open up ISE each time to convert the files into Verilog. Now I can do it with my bash script! It will save me quite a few steps.

Thanks, Craig

Yes, this works, and I can see the commands that Eilert referred to in his post! This will be very handy in the future if I can't figure out how the GUI is doing something!

Thanks, Craig.

Yes, I used xst as an example because I did not know the name of the tool to use. I though it might be xst because the schematic files are always converted inside the ISE GUI whenever I run the ISE simulator, and this is where xst is run to compile the verilog files.

Thanks for confirming this. You've saved a lot of time looking for a way to do something that cannot be done!

Regards, Craig