Hi
I have read on this group that it is required 4 pads space from LVDS differential signals to single-ended pin. Is this requirment concern also to PLL_OUTp/n pins?
PGW
Cyclone II - PLL differential output
Oct 08, 2007
2 Replies
pgw pisze:
Hi,
That's true. If you are not sure just try to fit it. But you can force this if LVDS is next to really slow signals like reset or slow I/O.
Adam
I have just do that. This requirment don't concern to PLL_OUT.
PGW
Join the Discussion
Have something to add? Share your thoughts — no account required.
Didn't find your answer?
Ask the community — no account required