Howdy Gurus,
I've seen the Xilinx Virtex 2 IOB documentation describing their LVDS i/o and their DDR i/o, but haven't found a clear explanation yet of the two being used together.
DDR by itself is pretty obvious, but the LVDS appears to work by a magical connection between two neighboring IOBs.
For an LVDS input pair (Dp and Dn) coming in at DDR, does the differential-to-single-ended conversion take place before the input flops of the IOB?
i.e., if Dp comes into IOB1 and Dn comes into IOB2, is there a single-ended output from some magical cell after the IOBs that I have to feed into two general CLB flops to get my registered Qre (rising edge) and Qfe (falling edge) outputs? (or specify an attribute to request that they be mapped into IOB flops?)
Or, if the conversion to single-ended is done before the IOB flops, then the single-ended DDR data is easily clocked into the two IOB flops on opposite clock edges, right?
If that is the case: Dp -> IPAD -> IOB1 ---\ (diff2single) >----- Dddr -----> to IOB flops Dn -> IPAD -> IOB2 ---/ (single-ended)
then which flops (those in IOB1 or IOB2) get the DDR data?
A clear explanation would be great, code/constraint snippets would be lovely!
Thanks,
MarkJ