LVDS output pins of Altera Cyclone II

Hi,

does anybody know how to switch of the LVDS output pins of a Cyclone II?

I use the "alt_lvds" megafunction but there are no inputs to this megafuction to enable or disable the LVDS output pins.

I thought about writing my own serializer as a workaround but I have no idea how this is done. But it should be possible by using the double data rate IOs and some shift registers.

Thanks.

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Anonymous
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Setting an output pin to LVDS is not part of the megafunction. You can use the assignment editor to accomplish what you want.

Writing your own serailizer usually takes a fairly good understanding of the hardware, setup/hold times, and jitter.

Reply to
Rob

Hi Rob,

I know that I have to use the assigment editor to change the output type from LVTTL (default) to LVDS.

But when using LVTTL I always have access to the "output enable" of the output pin to tri- state the pin. But this does not work when using LVDS output.

The output register is always enabled (OE set to '1') when I look at the design with the RTL viewer.

This is a little bit strange because actually the Cyclone II parts do not have any "real" LVDS outputs. It is standard LVTTL and the LVDS voltage levels are generated by a specific set of resitors on the PCB.

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Reply to
Anonymous

Why do you want to tri-state the LVDS outputs?

Reply to
Rob

I'm trying to use a FPGA to control a flat panel display that has LVDS inputs. Displays try to draw current from active LVDS lines if the power supply of the panel is switched off.

That is very harmful for the TFT and sooner or later it gets destroyed.

That is why I have to tri-state the LVDS outputs.

Every LVDS driver IC on the market has an "output enable" signal. So why shouldn't this be possible with an FPGA?

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Reply to
Anonymous

Didn't know that

Well, I know that a lot of Philips TFT panels are driven by a Cyclone II, but then again, these Cyclones get their current from the same supply as the panel so the TFT can try to draw current until it hurts, but the Cyclone will have nothing to give ;-)

Alternatively you could use SSTL2, which basically has the same electrical characteristics but is available as a bidirectional IO buffer. Setting OE to 0 in this mode would effectively tristate the buffer. Drive strength is limited to 15mA though.

Best regards,

Ben

Reply to
Ben Twijnstra

Hi,

thanks for the tip. I wrote my own serializer IP which uses the DDIOs as output stages and tristating the buffer works fine.

Best regards, Simon

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