We have an application where I need to feed 160 differential data inputs and 20 differential clock inputs to the high end V5 FPGA. There is one differential clock for every 8 differtnial data inputs. I would like to use LVPECL inputs for this.
160 differential data inputs will be running at 800Mbps20 Differenital clock inputs will be running at 400MHz. In order to provide DDR clock for 160 data channels.
Inside the FPGA we would like to use 1:4 demux and convert the data bus to 640 bits wide running at 200MHz so the FPGA fabric can handle it. Then the data will be fed to either 640 bits wide internal FIFO (as deep as I can get) or if I had a choice then feed the 640 bits wide bus running at 200MHz to external high density FIFO. This may require need for another FPGA.
I have seen Xilinx application note for supporting such configuration. But in our application we need a lot more data inputs.
I would like to get your input on this. Is this possible using high end V5 FPGA?
Thanks.