I've come to FPGAs from CPLDs and am rapidly realising that a reasonable (but not complete) knowledge of Verilog is not enough!
So tonight's question is:
How do I set up a balanced input?
I can write (a minimal example to make the point)
############ module top(Q, in, clk); output Q; input in; input clk; reg Q; always @(posedge clk) Q