Balanced inputs on Spartan3E

I've come to FPGAs from CPLDs and am rapidly realising that a reasonable (but not complete) knowledge of Verilog is not enough!

So tonight's question is:

How do I set up a balanced input?

I can write (a minimal example to make the point)

############ module top(Q, in, clk); output Q; input in; input clk; reg Q; always @(posedge clk) Q

Reply to
tersono
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If you are using a differential signal, like LVDS, you need to use a differential to single ended signal buffer. So, you would have two global "in" signals, in_P and in_N, which you assign pins to. Look at the FPGA's data sheet for examples of differential signal buffers. Then, "in" would be the output from the buffer.

---Matthew Hicks

Reply to
Matthew Hicks

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