Connecting different FPGAs using LVDS

Hi,

I am trying to connect a Virtex4 and a VirtexE FPGA by LVDS signals. When I look through oscilloscope I see a good signal however on Chipscope I see glitches. I am trynig to operate at about 1 MHz. For VirtexE side there is a 100 ohm termination resistor between differential lines at the receiver and there are 160 ohms and a 140 ohm at the transmitter sides and the connecting cable is matched 100 ohm cable (although it is a very short cable at about 25 cm = 10 inches). For Virtex4 I use Diff_term attribute at the receiver that's all. What can be the problem about this situation. I am stuck.

Thanks in advance.

Enes.

Reply to
Enes ERDIN
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Enes, this is not an answer but a question: Why do you plan to use LVDS for a short 1 MHz connection? Any single-ended (non-differential) standard would do this "hands- down". I do not see any inherent problem with LVDS, but why use two pins when one pin is enough? Peter Alfke, Xilinx Applications

Reply to
Peter Alfke

What constitutes a glitch?

How are you sourcing the clock and data? (using DDR flops, output registers, combinatorial outputs)

What edge are you using to clock the input data?

Do you have input timing constraints?

Are you using a DCM? If so, are you specifying SYSTEM_SYNCHRONOUS or SOURCE_SYNCHRONOUS?

I have a feeling the signal integrity is good, just an issue of system-level implementation.

- John_H

Reply to
John_H

Thank you for your answers. Sorry I have to be more precise. I am trying to implement the SpaceWire protocol. Unfortunately I have to use this link through a parallel cable for testing purposes (test setup is in that way and the cable is about 4 meters wihich includes also some D-sub connectors on it) So I am trying at such frequency. By the way when I implement two links on the same board and interconnect them they operate quite well but when I connect two different boards the link crashes.

Actually I have no idea as I said signal levels seem good when I observe in ossciloscope.

combinatorial outputs) Receiver clock is implemented through combinatorial logic (Data Strobe encoding). Transmitter clock is output registered.

For the receiver I use double edge

I have written the input constraints to the ucf file.

SOURCE_SYNCHRONOUS? I am not using a DCM

And an attached question : will it be a matter if I use VirtexE board supplied with (the bank is supplied) 3.3 V and Virtex4 is supplied with 2.5 V?

Thanks for your invaluable help.

Reply to
Enes ERDIN

registers, combinatorial outputs)

SOURCE_SYNCHRONOUS?

I also felt the need for writing the instantiation of the input and output buffers. Thanks.

===The instantiation for VirtexE bank is driven by 3.3 V === IBUF_LVDS_L1_DIN_P :IBUF_LVDS port map (I => L1_DIN_P, O =>

L1_DIN_int); IBUF_LVDS_L1_DIN_N :IBUF_LVDS port map (I => L1_DIN_N, O => open);

IBUF_LVDS_L1_SIN_P :IBUF_LVDS port map (I => L1_SIN_P, O =>

L1_SIN_int); IBUF_LVDS_L1_SIN_N :IBUF_LVDS port map (I => L1_SIN_N, O => open);

OBUF_LVDS_L1_DOUT_P : OBUF_LVDS port map (I=>L1_DOUT_int, O=>L1_DOUT_P); L1_DOUT_inv: INV port map (I=>L1_DOUT_int, O=>L1_DOUT_N_int); -- negative side OBUF_LVDS_L1_DOUT_N : OBUF_LVDS port map (I=>L1_DOUT_N_int, O=>L1_DOUT_N);

OBUF_LVDS_L1_SOUT_P : OBUF_LVDS port map (I=>L1_SOUT_int, O=>L1_SOUT_P); L1_SOUT_inv: INV port map (I=>L1_SOUT_int, O=>L1_SOUT_N_int); -- negative side OBUF_LVDS_L1_SOUT_N : OBUF_LVDS port map (I=>L1_SOUT_N_int, O=>L1_SOUT_N);

The UCF file: NET L1_DIN_P IOSTANDARD=LVDS; NET L1_DIN_N IOSTANDARD=LVDS; NET "L1_DIN_P" LOC = "P33"; NET "L1_DIN_N" LOC = "P34"; NET L1_SIN_P IOSTANDARD=LVDS; NET L1_SIN_N IOSTANDARD=LVDS; NET "L1_SIN_P" LOC = "P35"; NET "L1_SIN_N" LOC = "P36"; NET L1_DOUT_P IOSTANDARD=LVDS; NET L1_DOUT_N IOSTANDARD=LVDS; NET "L1_DOUT_P" LOC = "P52"; NET "L1_DOUT_N" LOC = "P53"; NET L1_SOUT_P IOSTANDARD=LVDS; NET L1_SOUT_N IOSTANDARD=LVDS; NET "L1_SOUT_P" LOC = "P38"; NET "L1_SOUT_N" LOC = "P39";

=======For Virtex4:=========

IBUFDS_L1_DIN : IBUFDS generic map ( CAPACITANCE => "NORMAL", -- "LOW", "NORMAL", "DONT_CARE" (Virtex-4 only) DIFF_TERM => TRUE, -- Differential Termination (Virtex-4, Spartan-3E/3A)----FALSE idi eskiden IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E/3A only) IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E/3A only) IOSTANDARD => "DEFAULT") port map ( O => L1_DIN, -- Clock buffer output I => L1_DIN_P, -- Diff_p clock buffer input (connect directly to top-level port) IB => L1_DIN_N -- Diff_n clock buffer input (connect directly to top-level port) );

--link1 sin IBUFDS_L1_SIN : IBUFDS generic map ( CAPACITANCE => "NORMAL", -- "LOW", "NORMAL", "DONT_CARE" (Virtex-4 only) DIFF_TERM => TRUE, -- Differential Termination (Virtex-4, Spartan-3E/3A)----------- IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E/3A only) IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E/3A only) IOSTANDARD => "DEFAULT") port map ( O => L1_SIN, -- Clock buffer output I => L1_SIN_P, -- Diff_p clock buffer input (connect directly to top-level port) IB => L1_SIN_N -- Diff_n clock buffer input (connect directly to top-level port) );

---------------------------------------------

----------------------------------------------

--link1 dout OBUFDS_L1_DOUT : OBUFDS generic map ( IOSTANDARD => "DEFAULT") port map ( O => L1_DOUT_P, -- Diff_p output (connect directly to top- level port) OB => L1_DOUT_N, -- Diff_n output (connect directly to top- level port) I => L1_DOUT -- Buffer input );

--link1 sout OBUFDS_L1_SOUT : OBUFDS generic map ( IOSTANDARD => "DEFAULT") port map ( O => L1_SOUT_P, -- Diff_p output (connect directly to top- level port) OB => L1_SOUT_N, -- Diff_n output (connect directly to top- level port) I => L1_SOUT -- Buffer input );

The UCF :

NET "L1_DIN_N" LOC = "Y18" | IOSTANDARD = LVDS_25 ; NET "L1_DIN_P" LOC = "AA18" | IOSTANDARD = LVDS_25 ; NET "L1_DOUT_N" LOC = "Y21" | IOSTANDARD = LVDS_25 ; NET "L1_DOUT_P" LOC = "Y20" | IOSTANDARD = LVDS_25 ; NET "L1_SIN_N" LOC = "W19" | IOSTANDARD = LVDS_25 ; NET "L1_SIN_P" LOC = "Y19" | IOSTANDARD = LVDS_25 ; NET "L1_SOUT_N" LOC = "W24" | IOSTANDARD = LVDS_25 ; NET "L1_SOUT_P" LOC = "W23" | IOSTANDARD = LVDS_25 ;

What if I use LVDS_25_DCI instead?

Reply to
Enes ERDIN

Dagnabbit. "When I look through oscilloscope I see a good signal however on Chipscope I see glitches." What the heck are you observing that makes you think your link isn't working? I repeat: What constitites a "glitch" in your problem statement?

isters, combinatorial outputs)

So the tx clock frequency is actually half the bit rate and the clock and data are both registered outputs from the same system clock? Did you verify these registers in the IOBs?

If your clock and data are both generated from the same master clock (as opposed to the TX clock generated from the falling edge and TX data generated from the rising edge of that master clock) then your timing constraints need to make sure there's a slightly negative hold time to avoid a hold violation. Your UCF information from the other post doesn't specify the timing constraints I asked about.

Please communicate these timing constraints for the Receive clock and data.

SOURCE_SYNCHRONOUS?

Thanks for that info.

The Virtex-E is specified for 2.5V drive. I expect your pad report tells you 2.5V Vcco is expected for that bank. It's not too much of an issue for the output LVDS, however, since the output networks are used to generate proper LVDS signal levels. You *are* using the recommended transmit termination scheme in the Virtex-E Functional Description "Design Considerations" section, aren't you? These values are ideally tweaked to give a different voltage swing but slightly overdriving your LVDS with a slightly higher common mode voltage is probably okay. Next time please design with the Vcco that the tools and data sheets recommend.

In the end, I wouldn't be surprised if your entire problem boils down to setup/hold violations at your input registers.

Are you using DDR input registers or implementing two registers that don't end up in the IOB?

- John_H

Reply to
John_H

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