I need some help with 'ChipScope Pro 6.3i inserter' in ISE 6.3.
As an exercise, I want to insert 'logic analyzer(ILA)' to simple 'counter' (below).
With respect to the user guide, I did was the following,
In ISE 6.3
- Bitstream generation and configuration on V2pro. ('counter.bit' - it seems okay)
After that, in 'ChipScope Pro Inserter' setting
- Input trigger setting : 3 triggers - One port for 'reset' signal(width 1), one port for 'count' signal(width 1), one port for 'Q' output signal (width 4) ) - Match type : 'Basic w/edge' type - Data type : "Data Same as Trigger"
- Connect - 'clock port' to 'CH0:clock_BUFGP' - 'trig0' to 'CH0:count_IBUF' - 'trig1' to 'CH0:reset_IBUF' - 'trig2' to 'CH0:Q_tmp_n0000, 'CH0:Q_tmp_n0000, 'CH0:Q_tmp_n0000, 'CH0:Q_tmp_n0000 - Insert ('counter.cdc' - it seems okay, but not quite sure)
After that, in 'ChipScope Pro Analyzer'
- Jtag Chain -> cable selection
- To configure FPGA, load 'counter.bit' to device 2.
- To import project file, load 'counter.cdc'
Then finally some waveform appears.
Problem is that I do not know how to set up 'input trigger ports' (in this case, 'count_IBUF', 'reset_IBUF', 'Q_tmp_n0000' - 5 signals ).
We need some input vectors (something like 'test vector' in simulation). So far :) I could not find how to do that in user guide.
Thankyou for reading and some comment too
---------------------------------------------------- library ieee ; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity counter is port( clock: in std_logic; reset: in std_logic; count: in std_logic; -- counter : enable Q: out std_logic_vector(3 downto 0) ); end counter;
architecture behv of counter is signal Q_tmp: std_logic_vector(3 downto 0); begin Q