ChipScope Pro : how to set up trigger


I need some help with 'ChipScope Pro 6.3i inserter' in ISE 6.3.

As an exercise, I want to insert 'logic analyzer(ILA)' to simple 'counter' (below).

With respect to the user guide, I did was the following,

In ISE 6.3

  • Implementation
  • Bitstream generation and configuration on V2pro. ('counter.bit' - it seems okay)

After that, in 'ChipScope Pro Inserter' setting

  • Input trigger setting : 3 triggers - One port for 'reset' signal(width 1), one port for 'count' signal(width 1), one port for 'Q' output signal (width 4) ) - Match type : 'Basic w/edge' type - Data type : "Data Same as Trigger"
  • Connect - 'clock port' to 'CH0:clock_BUFGP' - 'trig0' to 'CH0:count_IBUF' - 'trig1' to 'CH0:reset_IBUF' - 'trig2' to 'CH0:Q_tmp_n0000, 'CH0:Q_tmp_n0000, 'CH0:Q_tmp_n0000, 'CH0:Q_tmp_n0000 - Insert ('counter.cdc' - it seems okay, but not quite sure)

After that, in 'ChipScope Pro Analyzer'

  • Jtag Chain -> cable selection
  • To configure FPGA, load 'counter.bit' to device 2.
  • To import project file, load 'counter.cdc'

Then finally some waveform appears.

Problem is that I do not know how to set up 'input trigger ports' (in this case, 'count_IBUF', 'reset_IBUF', 'Q_tmp_n0000' - 5 signals ).

We need some input vectors (something like 'test vector' in simulation). So far :) I could not find how to do that in user guide.

Thankyou for reading and some comment too


---------------------------------------------------- library ieee ; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;

entity counter is port( clock: in std_logic; reset: in std_logic; count: in std_logic; -- counter : enable Q: out std_logic_vector(3 downto 0) ); end counter;

architecture behv of counter is signal Q_tmp: std_logic_vector(3 downto 0); begin Q

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"pasacco" schrieb im Newsbeitrag news:

its only you yourseld who knows on what event you want to trigger. just select the 1 0 R F B or in the trigger setting and arm the ILA

Antti BTW I dont understand why you defined 3 trigger ports not one, doesnt seem to make sense in this example.

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Antti Lukats


I am trying hard that 4 bit counter example with no luck so far --:

I changed into the following

In ILA Inserter

  • Trigger port : - number of port = 1, width = 1
  • Match function : - number of match unit = 2, match type = basic
  • Port connection - clock port
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try this link:

formatting link

it helped me a lot


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Thankyou for pointer. That document is quite nice. I followed the tutorial (Inserter and Analyzer) and got the (more ore less --:) same waveform as the tutorial.

ISE/ChipScopePro 6.3 has following differences (compared to version

4.2) among others.

- In 'Inserter', there is no ' Extended matching' button in 'Match setting' -----> So I ignored it.

- In 'Inserter', 'data depth' is minimally '512' -----> So I chose


- In 'Analyzer', there is no 'match length type' and 'match length value' in 'Trigger setting' -----> So i ignored it.

- In 'Analyzer', there is no 'capture type' -----> So i ignored it.

The waveform says that the counter logic is okay. Problem is that

- The waveform starts with the counter value "0011 0110 0101 0010" (with setting depth=512, position=100)

- At time '0', the counter value is "0011 0110 1011 0110", meaning first value + 100

Is it problematic?

BTW, I have two things unclear for me about 'match value' and 'position' in 'Trigger setup'.

Regarding the trigger condition : "00000001" < 2 match functions < "00000011"

- Is it correct that we make this condition in order to consider the 2 cycles of 'ILA' latency ?

Regarding 'position'

- In my case, . But in 'position' 100 (as indicated in the tutorial), the counter value is not "0000 0000 0000 0010", which was expected from the tutorial.

Anyway I wish to have "0000 0000 0000 0010" at time step '0'.

Thankyou again :) Regards

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Some trial and error (one match function == 2) for 4 bit counter case, now counter value is "0010" at time 0 (position=0). So it seems problem is solved. Thankyou again for comment and nice pointer. Regards

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