Hi
I have consulted the following link to initialize BRAM.
and it works fine for one BRAM module.
Problem is when I use 2 RAMB4_S4 components (each address 9 to 0, data
3 to 0), thus totally 1024 addresses and 8 bit data width.
Goal to initialize as follows
address 0 : X"08" -- opcode address 1 : X"71" address 2 : X"34" address 3 : X"95"
I am trying but MODELSIM simulation is showing unsatisfactory result so far ..... Could experienced one give comment for this?
-------------------------------------------------------------------- .=2E..
-- RAMB4_S4 declared ONCE as below component RAMB4_S4 generic ( INIT_00 : BIT_VECTOR :=3D X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : BIT_VECTOR :=3D X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : BIT_VECTOR :=3D X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : BIT_VECTOR :=3D X"0000000000000000000000000000000000000000000000000000000000000000" )
.=2E..
-- 2 components of RAMB4_S4 are instantiated TWICE as below RAM0: RAMB4_S4 generic map( INIT_00 =3D>
X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 =3D>
X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 =3D>
X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 =3D>
X"0000000000000000000000000000000000000000000000000000000000000000" ) port map(WE=3D>we, EN=3D>en, RST=3D>rst, CLK=3D>clk, ADDR=3D>addr, DI=3D>di= (3 downto 0), DO=3D>do(3 downto 0));
RAM1: RAMB4_S4 generic map( INIT_00 =3D>
X"0100000000000000000000000000000000000000000000000000000000000000", INIT_01 =3D>
X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 =3D>
X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 =3D>
X"0000000000000000000000000000000000000000000000000000000000000000" ) port map(WE=3D>we, EN=3D>en, RST=3D>rst, CLK=3D>clk, ADDR=3D>addr, DI=3D>di= (7 downto 4), DO=3D>do(7 downto 4));