init of FPGA's Block-RAMs.

It looks like you have what you need if you ignore the fact that there are

The question is where do you want to apply the INITs? The INITs work fine in the .ucf file. If you want them in your source code, you have to instantiate the BlockRAM primitive. Is that what you've done? In Verilog, I prefer to use the inline parameters rather than synthesis attributes or defparam values. One of these three methods will need to be used to attach the INITs properly to the instantiated BlockRAM. Which do you prefer?

If you're inferring your memory, look to your synthesizer's reference for initialization. An initial block will work for some synthesizers and Barry Brown pointed out how Synplify likes to handle file-based memory initialization for Verilog.

- John_H

The "first five addresses" are different for different BRAM data width setting, so it is hard to say whether your values in UCF is correct or not without knowing the bus width.

Cheers, Jim