xst synthesis with attributes failure

Aug 09, 2006 3 Replies

I have the following code which errors in 8.1.3 sw :



the error is something like ..actual value associated with a generic must be a globally static..



coef_2_rams : for i in 0 to 17 generate -- bit attribute RAM_INIT of inst : label is coef_init_2(i); begin inst: RAMD_OPREG generic map ( RAM_INIT => inst'RAM_INIT ) port map ( WADDR(3 downto 2) => "00", WADDR(1 downto 0) => etc


this is the logic being instantiated :



a_core : if true generate attribute INIT of ramd : label is RAM_INIT; begin ramd : RAM16X1D generic map ( INIT => str2suv(ramd'INIT) WADDR(2), a3 => WADDR(3),



str2suv is a function to convert a string to a logic_vector. This works if I do INIT => str2suv(RAM_INIT)



The problem looks to be the ramd'INIT I think.



The reason for doing this is to get a synthesis attibute and a generic for simulation without the error prone typing the value twice. The code compiles under Mentor Precision - and needs to keep doing so. Any ideas ?



The only solution I can think of it to have both :



attribute RAM_INIT of inst : label is coef_init_2(i)


*** and ***

RAM_INIT => coef_init_2(i)



Thanks for any ideas - and if XST people are reading this, any idea when this feature will be included ?? I have a very large number of these to change otherwise ...



/MikeJ


Hi Evan, thanks for your response.

The code was originally written for the Leonardo synthesiser, and at the time the synthesis attribute needed to be given as a string, but the simulation generic was a ulogic_vector. (We wrote our own simulation models for the primitives to support ulogic). Most of the INITs are static "2345" etc so to avoid possible errors between synthesis and simulation the 'init trick works quite well.

until XST that is ....

in this case RAM16X1D is a xilinx primitive, so I would have to put the "1234" in the generic as well I guess.

a_core : if true generate

found one solution, adding -- pragmas to stop XST seeing the problem :)

attribute INIT of mux4_lut1 : label is "00CA"; begin

mux4_lut1: LUT4 --pragma translate_off generic map ( lut => str2suv(mux4_lut1'INIT) ) --pragma translate_on port map ( I0 => DIN0(i),

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