Instantiating Altera M4K block without MegaWizard

Hi,

lpm_ram_* worked for me in the past.

But do you have to instantiate? If it s a single clock, you can write code that will infer to RAM blocks in both devices quite easily.

Cheers, Martin

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martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

Not to mention that using either lpm_ram_* or writing it yourself would make it portable between Xilinx and Altera and probably most other FPGA vendors and would not require any sort of generic to 'select' between the two non-portable options.

KJ

Hello,

If I'm not mistaken, lpm_ram_* is a MegaFunction. Or can you just write it down without running MegaWizard?

Best regards, Robert.

LPM is an EIA standard that is supported by several tool vendors. From what I've gathered though Altera was one of the main proponents of the standard...but that doesn't necessarily dilute the fact that it is an accepted and implemented standard. That said, it's not a terribly impressive set of functions but if you don't have the time to code your own fifos memories, multipliers and dividers it can be handy and portable.

KJ

LPM is an EIA standard that is supported by several tool vendors. From what I've gathered though Altera was one of the main proponents of the standard...but that doesn't necessarily dilute the fact that it is an accepted and implemented standard. That said, it's not a terribly impressive set of functions but if you don't have the time to code your own fifos memories, multipliers and dividers it can be handy and portable.

KJ

The more portable approach is to use Martin's suggestion.

But if you really want to find the Altera primitive just run through the MegaWizard to produce the VHDL file. Then simply open that file and take a look. What you'll likely find is that the MegaWizard produced file is a simple wrapper around the Altera primitive that you're interested in. From that you can search the Altera help for documentation on that primitive. The MegaWizard produced file will also obviously have an instantiation of that primitive with all of the generics set up per however it is that you answered things in the MegaWizard GUI.

KJ

Ah, I understand! And very little information to find on the subject indeed. Looks like the FPGA vendors really are not interested in supporting inter-vendor portability... Well, thanks for the info on LPM functions.

BR, Robert.

True, but the hdl synthesis manuals for ISE, Quartus, etc. do show the basic code templates, and most of these are portable.

-- Mike Treseler

There's a basic Altera-specific primitive called the ALTSYNCRAM. It's a generic synchronous RAM component that you can not only parametrize for width and depth, but also to only include M4Ks, what the maximum block depth is when generating a RAM block that is larger than an M4K etcetera.

It's pretty well-documented in the Quartus online help.

Best regards,

Ben

I'd like to turn the question around. Does Xilinx have something like ALTSYNCRAM? That is one module that is completely parameterizable, rather that a plethora of fixed dimension modules. Like the original post, I want to do it without coregen so that I can write parameterized code. Also, inferring doesn't seem to work because of mixed read and write widths, meaning in some cases the the end result will be a mix of RAM and luts.

I can't help snipped-for-privacy@gmail.com with the Xilinx question, but I thought I would chime in with some more Altera information and point you to documentation...

Previous posters are correct about manually modifying the Megafunction. I've seen designers do this when they have a lot of differently-sized memory blocks and they don't want to use the MegaWizard every time. There is some information about manually modifying a MegaWizard-generated file for memory in the Designing with Low_Level Primtives user guide:

See page 1-9 in the document or page 15 of the PDF (in document version 2.0). You can refer to Quartus II Help for more information about some of the parameters.

I would also agree with the folks that suggested inferring. That way your code is vendor-independent generic HDL! Although it is worth pointing out that the Altera and Xilinx memory architectures may be slightly different and by targeting the architecture (using registers where the device architecture is registered etc) you can often get better results and eliminate the need to create any logic outside the RAM to implement the exact functionality described in your HDL code. For examples of inferring RAM, refer to the Recommended HDL Coding Styles chapter of the Quartus II handbook at

RAM information starts on page 12 (in the 6.0.0 version of the document).

When you infer a RAM, the software will place it in the appropriate memory block for its size etc. If you want to drive an inferred RAM into a specific size of device memory (like an M4K specifically), Quartus II integrated synthesis provides the ramstyle synthesis attribute to specify the RAM type. Refer to Quartus II Integrated Synthesis chapter at

page 42 (in the 6.0.0 version of the document).

Jennifer Stephenson Altera

Re: LPMS: You'd hope so wouldn't you, but I've never had any joy getting LPMs into Xilinx without rewriting them as coregen blocks.

Xilinx: You *still* haven't got a way for me to instantiate arbitrarily sized (from generics) blocks of RAM like Altera let me! Grrr.

Instantating specific lumps of RAM blocks and wiring them up right is not my idea of fun. I know, I can do it once in a big generic'd wrapper that figures it out for me, but why should I have to? I then have to modify by wrapper each time a new size of RAM block comes along.

Cheers, Martin

--
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

Nope - I've ranted on this subject elsewhere (on a number of occasions)!

Sorry! Martin

--
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html