VHDL or Verilog

Hi clemens.... just go through the link below....

Hope it helps... bye

VHDL derives from Ada, Verilog from C. Consequently, VHDL is strongly typed. Some people like this (easier to catch errors), some don't (excessive complexity). It's largely a religious war.

Somehow, Verilog has come to be more p :Hello : :I have a very basic question. Normally you have the choice if you want to :use VHDL or Verilog for :describing you hardware architecture. I would be interested when do you :decide for VHDL and when for :Verilog. Are the special cases when it makes more sense to use one or the :other language? : :Thanks for helpful tips : :Clemens :

Muslim or Christian. Normally you have the choice of which you want to follow.....

Choice of HDL boils down mostly to a religious argument. Both have their plusses and minusses. Either will work fine for straight RTL coding. VHDL is more structured, and as a result is more verbose. The structure and verbosity bother some folks. Verilog is less precise, so although easier to code, it can let things slip through that are perhaps harder to find during integration. Verilog is also somewhat clumsy for generates with placement, but then the average designer doesn't do that. I use mostly VHDL because of the structural generation nature of a large portion of my work.

I find my self speechless, shocked that this thread hasn't deteriorated into a lengthy battle of people talking past each other, calling names and so on.

What's wrong with this group? Am I on the wrong Usenet???

Kind of like the battle of (pick any one you are familiar with).

Both armies on top of their respective hills can see the other side perfectly well, but got other business to attend to first.

regards