I am totally new to all this, so please forgive my naive questions.
I have a quartus project that runs on a development kit. All the pins are assigned and it works correctly. I wish to add an evaluation IP core, for which I have an .edif file (targeted for my fpga). How can I import this into my verilog project, and wont it potentially cause conflict with my existing pin assignments? What steps are generally taken to use an IP (edif) file?
There are also other (vhdl) files*, which I'm not sure why they were included, or if they should be added to my project. I know its impossible to tell with just a filename, so in general, what other files are normally needed to instantiate an IP core? Can VHDL files be added to a pure verilog project, or will this cause the instantiation to be troublesome?220model.vhd 220pack.vhd altera_mf.vhd altera_mf_components.vhd file.txt stratixii_atoms.vhd stratixii_components.vhd B_limited.vhd cpu_bfm_sital_ofer_hofman1.vhd executer_simple.vhd receiver_simple.vhd bus_tester.vhd textio.vhd textio_body.vhd tb_b_limited.vhd transceiver.vhd transmitter.vhd