I am interested in the compatibility of a VHDL project instantiating a verilog open core, floating point arthmetic block. Is this possible and if it is not is there another way to use a verilog open core inside a VHDL project, a transform of some kind?
VHDL Project Verilog open core compatibility?
Sep 29, 2004
1 Replies
Followup to: By author: snipped-for-privacy@spectrum.montana.edu (Cy Drollinger) In newsgroup: comp.arch.fpga
It depends on your software. Both Xilinx ISE and Altera Quartus support it just fine, but if you're using other tools it's up to each tool.
-hpa
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