Take verilog code from Xilinx Core generator

Hi Gordon,

The core generator > Hi everyone!

Thank you for your reply. But I can't modify it. Can you show me how to take the verilog code for synthesize? I would like to know how they process in this code.

There is no synthesizable verilog code from core generator. It only generate the netlist, verlog funtional simulation model and some template to instantiate the core in your toplevel design. You can take a look the _readme.txt for the detail generated files information.

If you d> >

It's a black box netlist. Your choices are

1. instance and use it as is, or
2. write and test your own code for synthesis.

-- Mike Treseler

I think you do not understand: There is no verilog code to take.

It is a "black-box macro"; the verilog wrapper just sets the parameters (configuration) of that macro.

You might be able to learn something by doing a gate level simulation, but that would be very tedious.

GH.

Thank you very much! I think I must design it. I have found document talk about DA for FIR filter.

Ahhh....

The perils of vendor "black box" or encrypted designs. They're difficult to simulate. Use them, and they lock you into a system. If there's a bug, you're dependent on the vendor to fix it.

There's a new EDA tool which makes clear text Verilog synthesizable source code for FIR filters (even testbenches for impulse, step, and random response), called the FIR HDL Writer from Optunis.

Here's a web link :

Hope this helps,

Tony