Hi
Can someone tell me if there is a defference between the following two VHDL sources working:
- process begin wait until C'event and C='1'; if B='0' then Q
A difference between VHDL sources working
Dec 29, 2003
2 Replies
It's apparent from the code: Case 1 says "wait for clock, THEN test B and act accordingly" Case 2 says "Test B, decide how to act, THEN wait for clock"
Also, Case A is synthesisable (be :Hi : :Can someone tell me if there is a defference between the following two VHDL :sources working: :1. :process :begin : wait until C'event and C='1'; : if B='0' then : Q
Yes.
Yes.
1 samples B and A just after the rising edge of C.2 samples B and A just after the rising edge of C, but doesn't use the value of B until after the next rising edge of C.
2 is not good coding style. Don't have more than one wait statement in a synthesisable process.
Yes. Try: The VHDL LRM. Any VHDL text book. Any VHDL lecture notes. The VHDL FAQ. Google.
Regards, Allan.
Join the Discussion
Have something to add? Share your thoughts — no account required.
Didn't find your answer?
Ask the community — no account required