Hi,
Can anybody please tell me what is wrong with the following code? In post-translate simulation there are a few unexpected short pulses. Thanks,
Alastair
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity divcontrol is port ( q : in std_logic_vector (7 downto 0); pulse, shift, rstout,ledinc,ledread: out std_logic ); end divcontrol;
architecture BEHAVIORAL of divcontrol is begin
with q select pulse
al99999 schrieb:
Your logic contains functional hazards.
I.e. if the input changes from 1 to 2 in 2s complement representation it will have the value 3 or 0 for a short time.
01 -> 11 -> 10 01 -> 00 -> 10Kolja Sulimma
hi,
If I were you, I prefer using synchronous LUT to get a clearer result using proces. So the change of the output signals are controlled by rising/falling edge of a clock signal. If you wanna use concurrent one, use D flip-flop to buffer the output signals, and to read the signal, use such a clock signal. I think it gives you better result. The drawback is the result doesn't come up instantly, delayed 1 clock period. Hope this help.
Ivan
al99999 wrote:
Have something to add? Share your thoughts — no account required.
Ask the community — no account required