following is a part of the state machine im trying to design. when start is set to '1' it goes to rw_1. when in that state, i increment the ram_counter_w and jumps to rw_2 , where the values of ram_counter_w is checked. if it is "11111111111111110", i jump to rw_3 , otherwise i come back to rw_1. The problem is i never go to rw_3. i continuously alternate between rw_1 and rw_2. Since im very new to VHDL and FPGA development, i cant find the problem. please someone help me.
Thank you CMOS
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type state_type is (ready, rw_1, rw_2, rw_3); signal state, next_state : state_type;
signal ram_counter_w : std_logic_vector(17 downto 0);
begin
process ( state, ram_counter_w) begin next_state if reset = '0' and start = '1' then next_state