vhdl state maching problem

following is a part of the state machine im trying to design. when start is set to '1' it goes to rw_1. when in that state, i increment the ram_counter_w and jumps to rw_2 , where the values of ram_counter_w is checked. if it is "11111111111111110", i jump to rw_3 , otherwise i come back to rw_1. The problem is i never go to rw_3. i continuously alternate between rw_1 and rw_2. Since im very new to VHDL and FPGA development, i cant find the problem. please someone help me.

Thank you CMOS

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type state_type is (ready, rw_1, rw_2, rw_3); signal state, next_state : state_type;

signal ram_counter_w : std_logic_vector(17 downto 0);

begin

process ( state, ram_counter_w) begin next_state if reset = '0' and start = '1' then next_state

Reply to
CMOS
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My first suggestion would be to declare the counter as an integer first so that the increment ('+') operation is more effective. Also the you can not use an IF statement to check a std_logic_vector since you would need to compare every single bit. Integer is easier to do so.

I gather this is an asynchronous state machine. There is no process for the clock. In this case you would only change states during each clock, and not on every time a bit changed as in your above example.

Reply to
pinod01

Hello Manusha,

I looked over your code and ran a simulation using the waveform tool in the Xilinx Webpack.

Some things:

1) You have no clock which is something I have never tried. Usually, VHDL is synchronous and you will see:

your_name : process(clk) begin if( clk'event and clk='1') then

starting most of your work.

2) You need a reset in your sensitivity list and an end process at the end of your process.

3) After simulating your code, your process never comes out of the the RESET state. Perhaps this is because next_state is not in your sensitivity list. You can try to put next_state in your sensitivity list, instead of state, but I don't know if that will solve your issues.

Good luck,

Brad Smallridge

P.S. Here is the code I ran:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity top is port( reset : in std_logic; start : in std_logic; state3 : out std_logic ); end top;

architecture Behavioral of top is

type state_type is (ready, rw_1, rw_2, rw_3); signal state, next_state : state_type;

signal ram_counter_w : std_logic_vector(17 downto 0);

begin

process (reset, state, ram_counter_w) begin next_state

Reply to
Brad Smallridge

Hello 'CMOS' It is usually a very bad idea to use a signal in the combinational process that updates it because it describes an asynchronous loop. I think you should use a synchronous process instead.

Nicolas

Reply to
Nicolas Matringe

I would second that ... Sorry about doing your homework....

1/ Synchronous counter desperately needs a clock.. you will get funny in between states when multiple bits transition simultaneously. And the state machine will quickly be in left field.

2/ Simulators need a reset.

3/ You need to assign state.. or better still, ignore next_state and just use state.

4/ Be nice to people who follow and give processes sensible names and add comments... no comments, no marks in my book

5/ what happens to ram_counter_w when it hits 131071 and wants to increment?

library ieee; use ieee.std_logic_unsigned.all;

type state_type is ( rw_1, rw_2, rw_3 ); signal state: state_type;

signal ram_counter_w: integer range 0 to 131071;

state_machine : process (clk) is begin -- add an async reset ?? or a synchronized reset

if rising_edge(clk) then

if ((reset = '1') or (start = '0')) then state It is usually a very bad idea to use a signal in the combinational

Reply to
Simon Peacock

thank you very much for all of your comments. i ll try proposed methods in a while. although i read a full book on introduction to VHDL for simulation and synthesis, i think i dont have enough knowledge to build a complex sysytem. the book i reead does not stress on the points you've mentioned here well. so im trying to find some good material on VHDL for sysnthesis ( specially for FPGA's ). If someone knows any resources, please let me know.

One other question. i got a book on "VHDL and AMS", which is about designing systems that might involve analog electronics as well. Im not sure about the extent to which this type of designing is used in the industry, so delaying reading of the book. Please if someone knows about of this, let me know..

Thank you CMOS

Reply to
CMOS

Additionally to all the remarks made by others, have you noticed that in

when rw_2 =>

if ram_counter_w = "11111111111111110" then next_state

Reply to
abeaujean

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