I'm building a multi-channel frequency synthesizer in a Xilinx XC2V6000-6 ES. I have verified a one and two channel build, but when I move to four channels the design stops working (slice usage goes from
12% with one channel to 50% with four). It looks as if the design is not clocking (all registers are returning '0' and there is no response to inputs). The only differences between the builds are the number of times the "channel module" is generated, a modification to a priority LUT, and a different adder to sum all the outputs of each "channel module". All timing constraints are met.
I have tried a number of things: Different reset logic on the DCMs, removing the DCMs altogether and just using the IBUFGs and BUFGs, using a non-ES version of the chip, etc. Nothing seems to work. Does anyone have any ideas?
Thanks
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