1. Home
  2. Field-Programmable Gate Arrays
  3. virtex-II problems

virtex-II problems

I'm building a multi-channel frequency synthesizer in a Xilinx XC2V6000-6 ES. I have verified a one and two channel build, but when I move to four channels the design stops working (slice usage goes from

12% with one channel to 50% with four). It looks as if the design is not clocking (all registers are returning '0' and there is no response to inputs). The only differences between the builds are the number of times the "channel module" is generated, a modification to a priority LUT, and a different adder to sum all the outputs of each "channel module". All timing constraints are met.

I have tried a number of things: Different reset logic on the DCMs, removing the DCMs altogether and just using the IBUFGs and BUFGs, using a non-ES version of the chip, etc. Nothing seems to work. Does anyone have any ideas?

Thanks

To send private email: snipped-for-privacy@cox.net where "xy" = "ed.agunos"

Reply to
ed
Loading thread data ...

Try looking in the Answers Database for ES "anomalies" that might be biting you. I searched on XC2V6000-6 ES and came up with a bunch of potential hits like this one regarding quadrant restrictions for IBUFG routing:

formatting link

There are other ES errata that apply to DCM usage, but you say that you've already tried running without DCMs.

Mark

ed wrote:

Reply to
Mark Schellhorn

Could well be incorrect logic produced by an error in the synthesiser.

I seem to be finding a lot of these recently.

Try running a post place and route simulation. to check for this, if possible.

Good Luck,

Ken, Morrow Electronics Limited.

biting you.

like this

formatting link

Reply to
Ken Morrow

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.