There is an utterly horrible VHDL howler on page of 45 of the latest Xcell Journal. Two example codes for a register with reset are given:
signal Q: std_logic:=?1?; ... async: process (CLK,RST) begin if (RST= ?1?) then Q
I should have added that this is also at:
--------------------------------------- Posted through
actually it should be sync: process (all) begin ... end process;
At least there was VHDL-2008 support announced for ISE11.1...
Kolja
Cute article. If only Xilinx would take some of their own advice on resets...
Tip #4 - Use active high control signals. (For some reason MIG defaults to active low reset).
Where's the tip on running your VHDL through syntax check before publishing it in a journal?
Cheers, Gabor
Listening for all synchronizes your RST with CLK. Right?
"process (all) is" not, AFAIK, supported yet by XST.
Anyway, if you want to know how to synchronize resets, read this paper:
--------------------------------------- Posted through
Ok. You used a tricky way to say that Kolja actually meant
_A_sync: process(all)
Hi All,
I am E Srikanth , and the author of the XCell Article " how do I reset my FPGA.
I accept that there were few errors in the article after that has been published. But the the errors have been fixed within few days after the day of publishing. Please download the pdf file again for all the corrections.
Regards, E Srikanth
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.