Do you have a question? Post it now! No Registration Necessary
Subject
- Posted on
August 7, 2003, 10:44 am

I tried this source code: <p>entity main is <BR>
Port ( clk , en : in std_logic; <BR>
sout : out
std_logic); <BR>
end main; <p>architecture Behavioral of main is <BR>
begin <BR>
process <BR>
variable a : std_logic; <BR>
begin <BR>
sout <= '0'; <BR>
a := '0'; <BR>
wait until rising_edge(en); <BR>
while en = '1' loop <BR>
-- wait until rising_edge(clk); <BR>
wait until clk'event and clk = '1'; <BR>
a := not a; <BR>
sout <= a; <BR>
end loop; <BR>
end process; <p>end Behavioral; <p>and I obtain this error:
<p>Analyzing Entity <main> (Architecture <behavioral>). <BR>
ERROR:Xst:825 - C:/Lavori/menfis/prova_xilinx/prova_2/main.vhd line xx: Wait
statement in a procedure is not accepted. <p>The question is: can I use wait or
not? <BR>
I found a lot of manual on the internet (eg. <a
href="http://mikro.e-technik.uni-ulm.de/vhdl/anl-engl.syn/html/node8.html )">http://mikro.e-technik.uni-ulm.de/vhdl/anl-engl.syn/html/node8.html )</a>,
and all of them sais that 'wait' is allowed in synthesis. <p>thanks
Port ( clk , en : in std_logic; <BR>
sout : out
std_logic); <BR>
end main; <p>architecture Behavioral of main is <BR>
begin <BR>
process <BR>
variable a : std_logic; <BR>
begin <BR>
sout <= '0'; <BR>
a := '0'; <BR>
wait until rising_edge(en); <BR>
while en = '1' loop <BR>
-- wait until rising_edge(clk); <BR>
wait until clk'event and clk = '1'; <BR>
a := not a; <BR>
sout <= a; <BR>
end loop; <BR>
end process; <p>end Behavioral; <p>and I obtain this error:
<p>Analyzing Entity <main> (Architecture <behavioral>). <BR>
ERROR:Xst:825 - C:/Lavori/menfis/prova_xilinx/prova_2/main.vhd line xx: Wait
statement in a procedure is not accepted. <p>The question is: can I use wait or
not? <BR>
I found a lot of manual on the internet (eg. <a
href="http://mikro.e-technik.uni-ulm.de/vhdl/anl-engl.syn/html/node8.html )">http://mikro.e-technik.uni-ulm.de/vhdl/anl-engl.syn/html/node8.html )</a>,
and all of them sais that 'wait' is allowed in synthesis. <p>thanks

Re: Xilinx ISE WebPack 5.2 & VHDL : wait synthesis

of

Your code is NOT a synthesable code.
Don't use 'wait' for synthesis code, but use 'wait' for your testbench
tester.
A synthesisable code will follow the rules:
- reset signal can be asynchro. or synchro.
- enable signal is ever synchro.
- if possible use only signal (don't use variable for synthesable code)
LOOK:
entity main is
Port ( clk , en : in std_ulogic;
sout : out std_ulogic);
end main;
architecture Behavioral of main is
signal a : std_ulogic;
begin
process (clk)
begin
if rising_edge(clk) then
if en = '1' then
a <= not a;
sout <= a;
end if ;
end if;
end process;
end Behavioral;
PS: 'wait' and 'variable' are GREAT for simulation
try http://www.amontec.com/vhdl_part.shtml
Laurent Gauch
www.amontec.com

Re: Xilinx ISE WebPack 5.2 & VHDL : wait synthesis

all of

Yeah, I would second that opinion. Reading your code it looks like you
are treating VHDL as a software language rather than a hardware
language. To see what I mean, consider what you are trying to tell the
compiler to generate. If you can't figure out what the hardware should
look like, how can you expect the software to figure it out? I know
that I can't figure out what hardware you are trying to describe or what
could be built that would do what your software does. It clearly does
not describe a FF with logic feeding the D input and a clock enable
signal. There are too many waits for that.
Take a look at some synthesis templates for FFs and other hardware items
that you might want to generate. Don't think in terms of the language,
think in terms of the hardware you want to build. Then you should get
synthesizable code.
--
Rick "rickman" Collins
snipped-for-privacy@XYarius.com
Rick "rickman" Collins
snipped-for-privacy@XYarius.com
We've slightly trimmed the long signature. Click to see the full one.
Site Timeline
- » Error Generate Statement
- — Next thread in » Field-Programmable Gate Arrays
-
- » OT: Offshore engineering
- — Previous thread in » Field-Programmable Gate Arrays
-
- » Fully Comitted to LVDS as Comparitors
- — Newest thread in » Field-Programmable Gate Arrays
-
- » [CHARTER] handvest nl.hobby.elektronica [maandelijks bericht, maart 2021]
- — The site's Newest Thread. Posted in » Electronics (Dutch)
-