Hello. Newbie here. I am trying to write a very simple program to simulate a multiplexer. I am using the xilinx version of the modelsim compiler viz. Modelsim XE version. heres my code:
library ieee; use ieee.std_logic_1164.all;
entity mux is port(a,b:IN std_logic_vector(7 downto 0); sel:IN std_logic_vector(1 downto 0); c : OUT std_logic_vector(7 downto 0)); end mux;
architecture example of mux is begin process(a,b,sel) begin if(sel = "00") then c
Hi,
different errors, have a close look at the following corrected code:
library ieee; use ieee.std_logic_1164.all;
entity mux is port(a,b:IN std_logic_vector(7 downto 0); sel:IN std_logic_vector(1 downto 0); c : OUT std_logic_vector(7 downto 0)); end mux;
architecture example of mux is begin process(a,b,sel) begin if(sel = "00") then c
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Hello. Tried the program which you had submitted. Worked correctly.However I have certain doubts which I'd like to clear. First of all, you removed the line where I associated the component muxc with the entity mux. Inspite of that it worked. Is it because your component and entity name were the same? Is this a kind of a rule wherein if the names of the component and the entity are the same then we need not explicitly link the entity with the given component?
Secondly when we use the port map clause the arguments are actuallp passed and substituted position-wise in the component right?
Well this is k> Hello .
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Yes, the default binding rule, but I find this as confusing as you did.
I prefer to eliminate the component completely and instance work.mux directly, like this:
architecture testbench of tb_mux is signal a,b,c : std_logic_vector(7 downto 0); signal sel : std_logic_vector(1 downto 0); begin M1: entity work.mux port map (a => a, -- IN b => b, -- IN sel => sel, -- IN c => c); -- OUT
Yes, that works, but I like the full mapping as above. Renaming the signal identifiers as a_s etc. is clearer still:
port map (a => a_s, -- IN b => b_s, -- IN sel => sel_s, -- IN c => c_s); -- OUT
-- Mike Treseler
Hello Mike. Thnks for letting me know that there are some people like myself who prefer clarity and simplicity. I know that VHDL - 93 allows one to completely do away with components but incase of VHDL - 87 , are we allowed to reference an entity directly as you did. So what would M1 be in such a case as you did. Normally M1 can be called an instant of the component in the "normal" case when we instantiate components but now as you haven't declared any components then what does M1 stand for. As far as I know we cannot have instances of entities (or can we??). Its getting a lil confusing here. would you kindly elaborate.
Secondly with regards to using the full mapping, do we have to place the target signals on the right hand side of the "=>" operator inside the port map clause brackets? Does this matter at all?
H> snipped-for-privacy@gmail.com wrote:
No, but any tool without -93 support is too old for serious use.
I might instance the entity more than once.
All instances are of entities.
Yes, yes.
-- Mike Treseler
As Mike says you should always instantiate components this way or when you get components of any size (10's of signals in/out) it becomes confusing trying to remember what's connected to what.
Nial.
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