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18 years ago
VHDL lub Verilog schemat
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18 years ago
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18 years ago
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18 years ago
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18 years ago
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18 years ago
tak w ogole to sadze, ze zdrowiej jest zadania domowe odrabiac samodzielnie, ale skoro na wiedczor ...
module reg74164 (clk, clr, A, B, Qa, Qb, Qc,Qd, Qe, Qf, Qg, Qh);
input clk, clr, A, B; output Qa, Qb, Qc,Qd, Qe, Qf, Qg, Qh;
reg [7:0] int_reg;
always @(posedge clk or negedge clr) begin if (!clr) int_reg <= 0; else begin int_reg <= {int_reg[6:0],(A&&B)}; end end
assign Qa = int_reg[0]; assign Qb = int_reg[1]; assign Qc = int_reg[2]; assign Qd = int_reg[3]; assign Qe = int_reg[4]; assign Qf = int_reg[5]; assign Qg = int_reg[6]; assign Qh = int_reg[7];
endmodule
JA
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18 years ago
Ciekawe jak to "kompilator" zrozumie .. domysli sie ze clr ma byc asynchroniczny ? :-)
J.
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18 years ago
"J.F." :
a czemu ma sie domyslac ? to jest standard w verilogu;
no i skompilowalem sobie ten kawalek, domyslil sie :)
JA