Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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Interfacing a circuit in an FPGA to a PC
If you have an interest in exchanging data between circuitry in an FPGA and= a PC, I have written a simple GUI that demonstrates transfers at full USB2= rates to and from an FPGA interfaced with an...
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11 years ago
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Neurons as the ultimate field programmable logic element, or Temporal displacement leads to spatial disorientation.
While discombobulating a sporadically, hideously dysfunctional fsm today, it occurred to me that I know exactly what that circuit feels. If it has a sense of purpose, that is, and cares about the...
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11 years ago
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Comparing virtex2 to spartan6
I know this is a question which is difficult to be answered, but does anyone have an estimate which Spartan-6 fpga has comparable 'size' as a xc2v1000 or a xc2v3000 fpga? With 'size' I don't mean chip...
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11 years ago
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FPGA and Package-on-Package
Since the Beagleboard and the Raspberry Pi use Package-on-Packge for integr= ating Flash and DRAM with the processor SoC I wonder why the FPGA vendors d= o not offer this. There are many FPGA-designs...
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11 years ago
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L3 protocol for transmission from small FPGA to embedded Linux system
Hi, I'd like to share with you my last development - a L3 protocol for transmission of data between low resources FPGA and an embedded system. It may allow you to use low cost/low resources FPGAs...
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11 years ago
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Re: Wow! No TestbenchWow!
Sorry I came in late for this one. I'm still quite new to VHDL external names. But I thought this is already possible with VHDL-2008? The simulatedUartTransmitter just looks like a package to me, with...
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11 years ago
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Tabula's fpga
Hi, does anybody here worked or know someone that worked with the tabula fpga device ? Are they much more efficient than competing fpga's ?
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11 years ago
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Smallest GPL UART
Hi all, I am searching for the smallest/simpler UART in verilog. I need to release the project under GPL and still confused about what are my options. I would go with micro UART by Jeung Joon Lee but...
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11 years ago
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FPGA Modular Firmware Skeleton for multiple instruments - Morph-IC-II, YouTube videos.
If you have an interest in using FPGAs for the design of instruments, this may be of interest : I have developed the following design as the framework for the bus interface of USB2 interfaced FPGA...
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11 years ago
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Platform Cable USB II in Windows 7 not Found (ISE 13.4)
Good morning, it is the first time I use a XILINX Platform Cable USB II together with Windows 7 , the problem is that the cable is not recognized and I've always the answer: " WARNING:iMPACT - The...
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11 years ago
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No bitstream generation on ISE 13.4 evaluation license
Good morning, I downloaded ISE 13.4 from Xilinx and installed on my pc to test an old Spartan 3A DSP 1800 Board, I installed an evaluation licence of 30 days, that I think includes bitstream...
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12 years ago
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FPGA circuit simulator
Hi, I wanted to know if there's any simulator like proteus for FPGAs, like where we can have a FPGA interfaced with some other ICs or LCD etc and without implementing it on hardware, we can see the...
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12 years ago
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New Merrick6 Version
From customer demand we are doing a cut down Merrick6 with only 2 way array XC6SLX150 FPGAs (without DDR fitted in array) plus the XC6SLX150T that controls the everything on the board. This new board...
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12 years ago
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Hard macros: can anybody give me practical advice?
Hello, The information that I find about hard macros is a little bit terse. What I= am missing mainly is how to get to a hard macro. This is nowhere specified= . Does one start from a simple VHDL...
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12 years ago
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VHDL syntheses timestamp
Hello all, I want to implement a "build" timestamp into some FPGA Designs (like the C __DATE__ makro). Optimal would be someting like the 32Bit unix timestamp. Does anybody know if there is some...
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12 years ago
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