Sorry I came in late for this one.
`timescale 1ns/1ns
>
>module simulatedUartTransmitter(output reg TxD);
> time bitTime;
> //
> task setBitTime(input time newBitTime);
> bitTime = newBitTime;
> endtask
>
> task sendChar(input [7:0] char);
> begin
> // send start bit
> TxD = 0;
> // send eight data bits, LSB first
> repeat (8) begin
> #(bitTime) TxD = char[0];
> char = char >> 1;
> end
> // send stop bit
> #(bitTime) TxD = 1;
> #(bitTime);
> end
> endtask
> //
> initial TxD = 1; // line idles in "Mark" state
> //
>endmodule
>
>module justTryThisOne;
> // connections
> wire serial_TxD;
> // stimulus generator instance
> simulatedUartTransmitter txGenerator(.TxD(serial_TxD));
> //
> // There's no DUT in this example, but you can still
> // see the signal generator at work.
> //
> // code to generate some stimulus
> initial begin
> txGenerator.setBitTime(104000); // 9600Bd, roughly
> #1_000_000; // idle awhile before starting
> txGenerator.sendChar("h"); // ask the sig-gen...
> txGenerator.sendChar("i"); // ...to send some data
> txGenerator.sendChar("!"); // ...at our request
> #1_000_000; // idle awhile at the end
> end
>endmodule
I'm still quite new to VHDL external names. But I thought this is already possible with VHDL-2008?
The simulatedUartTransmitter just looks like a package to me, with a few procedures:
library ieee; use ieee.std_logic_1164.all; package uartPkg is type simulatedUartTransmitter is protected procedure setBitTime(newBitTime:in time); procedure sendChar(char:in character); end protected simulatedUartTransmitter; signal TxD:std_ulogic; shared variable uartTx: simulatedUartTransmitter; end package uartPkg;
package body uartPkg is type simulatedUartTransmitter is protected body variable bitTime:time; procedure setBitTime(newBitTime:in time) is begin bitTime:=newBitTime; end procedure setBitTime; procedure sendChar(char:in character) is begin /* use wait statements to wait on bitTime. */ ... end procedure sendChar; end protected body simulatedUartTransmitter; end package body uartPkg;
/* The testbench. */ library ieee; use ieee.std_logic_1164.all; entity justTryThisOne is end entity justTryThisOne;
architecture noTestbenchInst of justTryThisOne is signal serial_TxD: std_ulogic; alias txGenerator is ;
begin tester: process is begin txGenerator.setBitTime(104000); wait for 1 us; txGenerator.sendChar('h'); txGenerator.sendChar('i'); txGenerator.sendChar('!'); wait for 1 us; end process tester; end architecture noTestbenchInst;
I haven't tried this with any simulator, but it might just work.
regards, daniel
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