Field-Programmable Gate Arrays

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The definition of combinatorial process?

The following topic may be one of the longest debate in vhdl group: http://groups.google.com/group/comp.lang.vhdl/brows...
0 comments posted 14yrs
posted by wtxwtx
0 comments posted 14yrs posted by wtxwtx

The definition of comnatorial prcess?

The following topic may be one of the longest debate in vhdl group: http://groups.google.com/group/comp.lang.vhdl/brows...
40 comments posted 14yrs
posted by wtxwtx
40 comments posted 14yrs posted by wtxwtx

Replacement for XC4005E

We've been using the venerable XC4005E FPGA from Xilinx for many years now in a bunch of products. However the variant...
12 comments posted 14yrs
posted by terry
12 comments posted 14yrs posted by terry

Modelsim MXE on wine?

I had MXE (Modelsim Xilinx Edition) running successfully under Wine until recently. However, following a lot of changes...
1 comments posted 14yrs
posted by nospam
1 comments posted 14yrs posted by nospam

RE: ADC problem on spartan3E

can i have ur vhdl code ...wid appreciate it a lot ... thanx in advance. my gmail: snipped-for-privacy@gmail.com
0 comments posted 14yrs
posted by zakaria.nits
0 comments posted 14yrs posted by zakaria.nits

Data transfers between MicroBlaze and VHDL

I am using EDK 14.1 and a Spartan-6 FPGA (potentially changing FPGAs in the future to the Artix 7 or Kintex 7). I am tr...
11 comments posted 14yrs
posted by robert.higginbotham0
11 comments posted 14yrs posted by robert.higginbotham0

Fpga to Asic conversion, firm list and prices.

Maybe is time write more about price and about firm specialized in PGA-to-ASIC replacement. Please, add company name an...
1 comments posted 14yrs
posted by kwiateq0007
1 comments posted 14yrs posted by kwiateq0007

FPGA FIFO MAX data speed

hi, guys: i'm designing a fifo using XILINX FPGA V6. the fifo will be used to transport data between ARM11(OR POWERPC)...
2 comments posted 14yrs
posted by yuzhe_zhang
2 comments posted 14yrs posted by yuzhe_zhang

Virtex 4 Cameralink DCM Limitation

I have a cameralink (LVDS SERDES) I'm trying to capture data with using a Virtex 4 mature product. I have ported the XA...
11 comments posted 14yrs
posted by d.cooke
11 comments posted 14yrs posted by d.cooke

Reading out LUTM content

Hi all, Following problem: We have an Xilinx Virtix 5, having an implementation running on it. What we want to do, is t...
0 comments posted 14yrs
posted by reinhard.haemmerle
0 comments posted 14yrs posted by reinhard.haemmerle

FPGA Interconnect

Hi, Here is a question little bit in the internals of the FPGA. I am asking this more out of my curiosity and learning....
3 comments posted 14yrs
posted by bukka4
3 comments posted 14yrs posted by bukka4

TCE 1.6

TTA-based Co-design Environment (TCE) v1.6 released --------------------------------------------------- TTA-based Co-de...
0 comments posted 14yrs
posted by pekka.jaaskelainen
0 comments posted 14yrs posted by pekka.jaaskelainen

MPMC does not finish initialization in simulation

Hello Friends, I am working on virtex6. I am trying to debug a problem by simulating in modelsim. But in the simulation...
2 comments posted 14yrs
posted by toshubhendu
2 comments posted 14yrs posted by toshubhendu