Latest threads in Field-Programmable Gate Arrays

Interfacing a circuit in an FPGA to a PC

If you have an interest in exchanging data between circuitry in an FPGA and= a PC, I have written a simple GUI that dem...

2 14yrs

j.b.w.webber

2 14yrs j.b.w.webber

Neurons as the ultimate field programmable logic element, or Temporal displacement leads to spatial disorientation.

While discombobulating a sporadically, hideously dysfunctional fsm today, it occurred to me that I know exactly what th...

0 14yrs

boat042-nospam

0 14yrs boat042-nospam

Comparing virtex2 to spartan6

I know this is a question which is difficult to be answered, but does anyone have an estimate which Spartan-6 fpga has...

4 14yrs

theller

4 14yrs theller

FPGA and Package-on-Package

Since the Beagleboard and the Raspberry Pi use Package-on-Packge for integr= ating Flash and DRAM with the processor So...

1 14yrs

acd4usenet

1 14yrs acd4usenet

L3 protocol for transmission from small FPGA to embedded Linux system

Hi, I'd like to share with you my last development - a L3 protocol for transmission of data between low resources FPGA...

0 14yrs

wzab

0 14yrs wzab

Re: Wow! No TestbenchWow!

Sorry I came in late for this one. >`timescale 1ns/1ns > >module simulatedUartTransmitter(output reg TxD); > time bitTi...

2 14yrs

daniel.kho

2 14yrs daniel.kho

Tabula's fpga

Hi, does anybody here worked or know someone that worked with the tabula fpga device ? Are they much more efficient than...

0 14yrs

ippisl

0 14yrs ippisl

Smallest GPL UART

Hi all, I am searching for the smallest/simpler UART in verilog. I need to release the project under GPL and still conf...

28 14yrs

giuseppe.marullonospam

28 14yrs giuseppe.marullonospam

FPGA Modular Firmware Skeleton for multiple instruments - Morph-IC-II, YouTube videos.

If you have an interest in using FPGAs for the design of instruments, this may be of interest : I have developed the fo...

0 14yrs

j.b.w.webber

0 14yrs j.b.w.webber

Platform Cable USB II in Windows 7 not Found (ISE 13.4)

Good morning, it is the first time I use a XILINX Platform Cable USB II together with Windows 7 , the problem is that t...

3 14yrs

postmaster

3 14yrs postmaster

No bitstream generation on ISE 13.4 evaluation license

Good morning, I downloaded ISE 13.4 from Xilinx and installed on my pc to test an old Spartan 3A DSP 1800 Board, I inst...

2 14yrs

postmaster

2 14yrs postmaster

FPGA circuit simulator

Hi, I wanted to know if there's any simulator like proteus for FPGAs, like where we can have a FPGA interfaced with som...

2 14yrs

a1234573

2 14yrs a1234573

New Merrick6 Version

From customer demand we are doing a cut down Merrick6 with only 2 way array XC6SLX150 FPGAs (without DDR fitted in arra...

0 14yrs

g1

0 14yrs g1

Hard macros: can anybody give me practical advice?

Hello, The information that I find about hard macros is a little bit terse. What I= am missing mainly is how to get to...

0 14yrs

jurgen.defurne

0 14yrs jurgen.defurne

VHDL syntheses timestamp

Hello all, I want to implement a "build" timestamp into some FPGA Designs (like the C __DATE__ makro). Optimal would be...

19 14yrs

arne

19 14yrs arne

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