Field-Programmable Gate Arrays

Comparing virtex2 to spartan6

I know this is a question which is difficult to be answered, but does anyone have an estimate which Spartan-6 fpga has...

4 comments posted 14yrs

posted by theller

4 comments posted 14yrs posted by theller

FPGA and Package-on-Package

Since the Beagleboard and the Raspberry Pi use Package-on-Packge for integr= ating Flash and DRAM with the processor So...

1 comments posted 14yrs

posted by acd4usenet

1 comments posted 14yrs posted by acd4usenet

L3 protocol for transmission from small FPGA to embedded Linux system

Hi, I'd like to share with you my last development - a L3 protocol for transmission of data between low resources FPGA...

0 comments posted 14yrs

posted by wzab

0 comments posted 14yrs posted by wzab

Re: Wow! No TestbenchWow!

Sorry I came in late for this one. >`timescale 1ns/1ns > >module simulatedUartTransmitter(output reg TxD); > time bitTi...

2 comments posted 14yrs

posted by daniel.kho

2 comments posted 14yrs posted by daniel.kho

Tabula's fpga

Hi, does anybody here worked or know someone that worked with the tabula fpga device ? Are they much more efficient than...

0 comments posted 14yrs

posted by ippisl

0 comments posted 14yrs posted by ippisl

Smallest GPL UART

Hi all, I am searching for the smallest/simpler UART in verilog. I need to release the project under GPL and still conf...

28 comments posted 14yrs

posted by giuseppe.marullonospam

28 comments posted 14yrs posted by giuseppe.marullonospam

FPGA Modular Firmware Skeleton for multiple instruments - Morph-IC-II, YouTube videos.

If you have an interest in using FPGAs for the design of instruments, this may be of interest : I have developed the fo...

0 comments posted 14yrs

posted by j.b.w.webber

0 comments posted 14yrs posted by j.b.w.webber

Platform Cable USB II in Windows 7 not Found (ISE 13.4)

Good morning, it is the first time I use a XILINX Platform Cable USB II together with Windows 7 , the problem is that t...

3 comments posted 14yrs

posted by postmaster

3 comments posted 14yrs posted by postmaster

No bitstream generation on ISE 13.4 evaluation license

Good morning, I downloaded ISE 13.4 from Xilinx and installed on my pc to test an old Spartan 3A DSP 1800 Board, I inst...

2 comments posted 14yrs

posted by postmaster

2 comments posted 14yrs posted by postmaster

FPGA circuit simulator

Hi, I wanted to know if there's any simulator like proteus for FPGAs, like where we can have a FPGA interfaced with som...

2 comments posted 14yrs

posted by a1234573

2 comments posted 14yrs posted by a1234573

New Merrick6 Version

From customer demand we are doing a cut down Merrick6 with only 2 way array XC6SLX150 FPGAs (without DDR fitted in arra...

0 comments posted 14yrs

posted by g1

0 comments posted 14yrs posted by g1

Hard macros: can anybody give me practical advice?

Hello, The information that I find about hard macros is a little bit terse. What I= am missing mainly is how to get to...

0 comments posted 14yrs

posted by jurgen.defurne

0 comments posted 14yrs posted by jurgen.defurne

VHDL syntheses timestamp

Hello all, I want to implement a "build" timestamp into some FPGA Designs (like the C __DATE__ makro). Optimal would be...

19 comments posted 14yrs

posted by arne

19 comments posted 14yrs posted by arne

ICTP Open Hardware Initiative – Invitation to part icipate in an open-survey.

Dear Colleagues / Friends We would like to invite you to participate in an important survey regarding an open FPGA Hard...

0 comments posted 14yrs

posted by ictpmlab

0 comments posted 14yrs posted by ictpmlab

recomendation on a processor core

hi, after few years i want to restart FPGA development once again - initially f= or personel fun, but later may move in...

7 comments posted 14yrs

posted by manusha1980

7 comments posted 14yrs posted by manusha1980