FPGA and Package-on-Package

grating Flash and DRAM with the processor SoC I wonder why the FPGA vendors= do not offer this. There are many FPGA-designs that need external memory a= nd the pins to the base PCB are valuable resource.=20

d it, as far as I could find.=20

that integrates with them would expand that spectrum.=20

hange.=20

Xilinx has dropped some hints on this, but I think the bigger issue, is th= e FPGA is FAR LESS price sensitive, and MORE performance sensitive, than th= e products that use Stacked-Die.

So, the top end FPGA's simply add more on chip RAM, and sell you a bigger = part!!

You are quite right tho, that there is an opening for a smaller FPGA, or l= arger CPLD, tightly coupled to RAM.

Even here, the issue is volume, as the really big players like Broadcom, c= an get good enough performance from their Stacked approach, to tackle 98% o= f the high volume markets - that leaves the crumbs for the PLD vendor.