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- Date
- Subject
- Replies
- 10-12-2004
- level converter for high frequencies
- 3
- 10-12-2004
- EP1C12 or XC3S400? [ 2 ]
- 30
- -
- 10-12-2004
- Initializing Block Ram of a partial Bitstream
- 0
- -
- 10-12-2004
- xilinx VP20 and SDRAM
- 0
- 10-12-2004
- direct calculation of the modulus ?
- 9
- 10-12-2004
- Reading RAM while
- 3
- 10-12-2004
- DCM for generating higher frequencies.
- 3
- 10-12-2004
- newbie question
- 2
- 10-11-2004
- Re: CAche memory
- 1
- 10-11-2004
- multiplexing clocks
- 10
- 10-11-2004
- Student SATA project
- 4
- 10-11-2004
- GLKP and GLKS
- 4
- 10-11-2004
- Xilinx Spartan3 config problem
- 3
- 10-11-2004
- low cost MPEG4 codec (from Atmel )
- 5
- -
- 10-11-2004
- Unguided slices
- 0
- -
- 10-11-2004
- Multiple Access on long lines
- 0
- 10-11-2004
- CORDIC NCO Frequency resolution?
- 3
- 10-11-2004
- Actel Fusefile Reverse Engineering
- 6
- 10-11-2004
- Routing PLL output
- 9
- -
- 10-11-2004
- Micromechatronics, is there money in this area?
- 0
- 10-10-2004
- Problem in Constraining Routing in Xilinx PAR
- 3
- 10-10-2004
- VHDL help needed ($)
- 3
- 10-10-2004
- Temperature considerations of inactive logic blocks
- 3
- -
- 10-10-2004
- MXE post-translate simulation problem
- 0
- 10-10-2004
- VHDL code for Type and Components
- 2
- 10-10-2004
- Newbie, Altera vs Xilinx
- 2
- -
- 10-10-2004
- Xilinx : Memory-Compiler for DDR-1
- 0
- 10-10-2004
- Coregen difficulties with DCT
- 2
- 10-10-2004
- Daft RapidIO question
- 2
- -
- 10-09-2004
- RapidIO functional simulation
- 0
- 10-09-2004
- Use Xilinx VP20 with 2 ppc and one DRAM chip
- 6
- 10-08-2004
- Spartan 3 Kit
- 4
- -
- 10-08-2004
- PPC cores and XAUI core on Xilinx Virtex-II Pro 20
- 0
- 10-08-2004
- Sine function implementation in FPGA
- 2
- 10-08-2004
- Daft modelsim question
- 3
- -
- 10-08-2004
- 3.3 V ref VCC on Xilinx AFX FF1152 board?
- 0
- 10-08-2004
- Flex10K10A, I2C, MultiVolt IO, pull-ups
- 5
- 10-08-2004
- Xilinx DCM and Timing Constraints
- 6
- 10-07-2004
- Xilinx lead free parts hidden fact
- 2
- 10-07-2004
- add/sub 2:1 mux and ena in a single LE (Cyclone)
- 11
- 10-07-2004
- PLL lock usage into Altera Stratix devices
- 3
- 10-07-2004
- modelsim crashs with large ram simulation model
- 3
- 10-07-2004
- Synplify on Fedora C2
- 4
- -
- 10-07-2004
- International Workshop on Applied Reconfigurable Computing (ARC): 2nd call for papers
- 0
- 10-07-2004
- XILINX SHIPS ONE MILLION SPARTAN-3 FPGAS
- 7
- 10-07-2004
- Unused pins
- 1
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