Latest threads in Field-Programmable Gate Arrays

fixed point fft butterfly stage testing help

I am new to verilog/hardware arithmetic and seeking good advice on testing a fft butterfly stage that I have written. m...

0 14yrs

jack.pett.son

0 14yrs jack.pett.son

Spartan 6 MCB refresh timing

Hi there, I'm designing a memory solution with a Spartan 6 talking to 2 128MByte 16-bit-wide DDR3 RAMs. As my applicati...

3 14yrs

stefan

3 14yrs stefan

modelsim SE 10.0C SystemC bug about initializing sc_signal

I am very disappointed that I get different results from the same initializing code in SC_CTOR from 6.6 and 10.0 versio...

2 14yrs

3749

2 14yrs 3749

FPGA-Board for Ethernet

Hi, I am searching a FPGA board for a project where i have to connect an twiste d pair cable to a FPGA and send&receive...

6 14yrs

bln5320

6 14yrs bln5320

fft in fpga using polar form

i understand that representing large number of twiddle factors that are req uired in a fft with large number of points...

2 14yrs

jack.pett.son

2 14yrs jack.pett.son

Need Terasic LTM Module

Hi, I delayed too long in ordering a Terasic LTM touchscreen module and now they are listed as phased out with no substi...

0 14yrs

abbybrown

0 14yrs abbybrown

JTAG access from user design in Altera FPGAs

Hi, does somebody know, how to access the JTAG port from a user design (VHDL) in Altera FPGA (cyclone 4)? TIA Ludwig

2 14yrs

spamtrap-lh-0506

2 14yrs spamtrap-lh-0506

Replacing Logic with an FPGA/CPLD in a 510K device.

Does anyone have some good links on FDA requirements for replacing TTL logic with an FPGA/CPLD ? This is for a Class 3...

2 14yrs

hamilton

2 14yrs hamilton

Multiple IDELAYCTRLs in V-5: how, and why?

I'm on Virtex-5, and have a lot of IODELAYs, for fixed and variable input delays. I've read chapter 7 of the User Guide...

1 14yrs

nospam

1 14yrs nospam

Just gloating

I've got a VHDL design in which I use record types as a convenient way of wiring up my internal buses. This design is a...

1 14yrs

rgaddi

1 14yrs rgaddi

edge matching

Hello 1. I'am a beginner in fpga.and want some help. I'am trying to write code for matching rising edges of two differe...

1 14yrs

3698

1 14yrs 3698

Getting in to the industry

Hi, I'm new to FPGAs but would like to get into the industry. Aside from building and playing around with toy projects,...

4 14yrs

3681

4 14yrs 3681

Error while running implementation through unix command line

Hello, I am new to Xilinx and bash scripting. I am using Xilinx 13.4. I am trying to run implementation(ngdbuild, map,...

6 14yrs

3677

6 14yrs 3677

How to estimate PEAK power consumption on Xilinx FPGA ?

Hi, Is there anyway to estimate "PEAK power consumption" using an Xilinx XPower analyzer ? I think the "Summar" page sh...

1 14yrs

3676

1 14yrs 3676

JTAG3-parallel cable on SPARTAN-3 digilent Starter kit

Hi all, I have been trying to make the JTAG3-parallel cable with SPI work with spartan-3 board on red-hat linux(both fr...

0 14yrs

3667

0 14yrs 3667

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