How do you set up search paths in Vivado so that it will find `includes files? XST supported incdir (in the form of the -vlgincdir switch). I haven't found an incdir in the Vivado documentation, does anyone know what the tcl command is for incdir?
Is it the 'add_files -scan_for_includes PATH' ?
In the TCL doc: scan_for_includes: Scan and add any included files found in the fileset's RTL sources
I work around the problem by having my build script parse the project file, identify all verilog files (we use mixed VHDL / Verilog for some projects here), and for each verilog file, parse it, identify the include files, and then copy the include files into the current directory of the compiler.
This works with XST. I imagine it would work with just about any tool, incuding Vivado.
Personally, I blame the original Verilog authors, who neglected to make Verilog's `include work like C's #include.
Verilog: (AIUI) the LRM does not define how `include files are located, and compilers will use locations relative to the cwd of the tool.
C: #include "file" will be relative to the location the file being compiled.
Regards, Allan
I don't think that's it. The incdir command in Verilog sets up the search path order. For example in an XST script,
-vlgincdir { "./in" "./v" "../v" "../../../../common/hdlmaker/v" }
The scan_for_includes looks like it tells Vivado to do something that it should always do anyway which is read in the `includes.
When I use ISE, I generally have a project file structure where theres a main folder, and under that I have a "synth" or "ise" folder where the ISE project file resides, and where all the crap that ISE leaves behind resides. My source is in a "source" or "src" folder, cores are in a "cores" folder, etc. Then if I use `include, I use a relative path like:
`include "../include/my_stuff.h"
And because of the structure, this relative path is the same whether looking from the "synth" directory or the "source" directory. ISE in fact looks in the directory where the project file (.xise) resides but paths relative to that also work.
I haven't looked at how this works in Vivado, but it's probably similar.
-- Gabor
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I don't know how to do it as a TCL command, but know how to do it from Viva do GUI: you should press Project Settings, you will be at the General Setti ngs group. At the bottom line "Language options" you should press "..." but ton from the right. Then press "..." button at the up-most line "Verilog op tions" and you will see the "Verilog include files search paths" field. Tha t's it )
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