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Spartan 6 IBERT confusion

If I use the core generator to generate an IBERT for a Spartan 6 and try to= implement the example design the errors I'm getting I'm not understanding.= I'm assuming I'm not understanding the back box portion of the example des= ign. Module S6chipscope_ibert.v is in the project. Thanks in advance... He= re are the errors, followed by the example design:

ERROR:NgdBuild:604 - logical block 'U_S6CHIPSCOPE_IBERT' with type 'S6chipscope_ibert' could not be resolved. A pin name misspelling can ca= use this, a missing edif or ngc file, case mismatch between the block name a= nd the edif or ngc file name, or the misspelling of a type name. Symbol 'S6chipscope_ibert' is not supported in target 'spartan6'. ERROR:NgdBuild:604 - logical block 'U_ICON' with type 'chipscope_icon' coul= d not be resolved. A pin name misspelling can cause this, a missing edif or ng= c file, case mismatch between the block name and the edif or ngc file name= , or the misspelling of a type name. Symbol 'chipscope_icon' is not supported= in target 'spartan6'.

`timescale 1ns / 1ps //***************************** Module **************************** module example_S6chipscope_ibert ( //Input Declarations input GTP0_X0_Y0_RX_P_IPAD, input GTP0_X0_Y0_RX_N_IPAD, input GTP1_X0_Y0_RX_P_IPAD, input GTP1_X0_Y0_RX_N_IPAD, input SYSCLOCK_P_IPAD, input SYSCLOCK_N_IPAD, input REFCLK0_X0Y0_P_IPAD, input REFCLK0_X0Y0_N_IPAD, //Output Decalarations output GTP0_X0_Y0_TX_P_OPAD, output GTP0_X0_Y0_TX_N_OPAD, output GTP1_X0_Y0_TX_P_OPAD, output GTP1_X0_Y0_TX_N_OPAD

);

//local signals declaration wire refclk0_x0y0_i; wire ibert_sysclock; wire [35:0] CONTROL0; // Ibert Core Wrapper Instance S6chipscope_ibert U_S6CHIPSCOPE_IBERT ( .GTP0_X0_Y0_TX_P_OPAD(GTP0_X0_Y0_TX_P_OPAD), .GTP0_X0_Y0_TX_N_OPAD(GTP0_X0_Y0_TX_N_OPAD), .GTP1_X0_Y0_TX_P_OPAD(GTP1_X0_Y0_TX_P_OPAD), .GTP1_X0_Y0_TX_N_OPAD(GTP1_X0_Y0_TX_N_OPAD), .GTP0_X0_Y0_RX_P_IPAD(GTP0_X0_Y0_RX_P_IPAD), .GTP0_X0_Y0_RX_N_IPAD(GTP0_X0_Y0_RX_N_IPAD), .GTP1_X0_Y0_RX_P_IPAD(GTP1_X0_Y0_RX_P_IPAD), .GTP1_X0_Y0_RX_N_IPAD(GTP1_X0_Y0_RX_N_IPAD), .REFCLK0_X0Y0_I(refclk0_x0y0_i), .CONTROL(CONTROL0), .SYSCLOCK_I(ibert_sysclock) );

chipscope_icon U_ICON ( .CONTROL0(CONTROL0));

// GT Refclock Instances =20 IBUFDS U_TILE0_REFCLK0 ( .O(refclk0_x0y0_i), .I(REFCLK0_X0Y0_P_IPAD), .IB(REFCLK0_X0Y0_N_IPAD) ); =20 =20 // Sysclock Source IBUFDS U_SYSCLOCK_IBUFDS ( .O(ibert_sysclock), .I(SYSCLOCK_P_IPAD), .IB(SYSCLOCK_N_IPAD) );

endmodule

// Black box declaration module S6chipscope_ibert ( output GTP0_X0_Y0_TX_P_OPAD, output GTP0_X0_Y0_TX_N_OPAD, output GTP1_X0_Y0_TX_P_OPAD, output GTP1_X0_Y0_TX_N_OPAD, input GTP0_X0_Y0_RX_P_IPAD, input GTP0_X0_Y0_RX_N_IPAD, input GTP1_X0_Y0_RX_P_IPAD, input GTP1_X0_Y0_RX_N_IPAD, input REFCLK0_X0Y0_I, inout [35:0] CONTROL, input SYSCLOCK_I ); endmodule module chipscope_icon ( inout [35:0] CONTROL0); endmodule

Reply to
pminmo
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implement the example design the errors I'm getting I'm not understanding. I'm assuming I'm not understanding the back box portion of the example design. Module S6chipscope_ibert.v is in the project. Thanks in advance... Here are the errors, followed by the example design:

not

or

Do you have the .ngc file for the ibert module in the project directory? It contains the actual module guts.

Good Luck, BobH

Reply to
BobH

y to implement the example design the errors I'm getting I'm not understand= ing. I'm assuming I'm not understanding the back box portion of the example= design. Module S6chipscope_ibert.v is in the project. Thanks in advance..= . Here are the errors, followed by the example design:

an cause

ame and

l

could not

or ngc

name, or

orted in

=20

Yes, I've tried the ngc file(s) with no luck.

Reply to
Phil

implement the example design the errors I'm getting I'm not understanding. I'm assuming I'm not understanding the back box portion of the example design. Module S6chipscope_ibert.v is in the project. Thanks in advance... Here are the errors, followed by the example design:

cause

and

not

ngc

name, or

supported in

It really sounds like the .ngc files are not where they can be found by the tool. The .v file is only a wrapper/prototype for the contents in the .ngc file. Is the .ngc file for the ibert in the project top level directory (where the log files and .pcf file wind up) and the .ngc name matches the one instantiated in your RTL file? I think that there is a place in the project properties page where you can explicitly tell it where to find the .ngc files. Another possibility would be if you added the .v file to the project after the project was defined, did it go into the same library as the rest of your RTL? If you look in the files window on ISE and scroll to the right, past the end of the file names, it will tell you which library a file went into. I spent 3 days fighting an issue like this, only to find that the file went into a different library and did not get included in the synthesis.

Good Luck, BobH

Reply to
BobH

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