Field-Programmable Gate Arrays

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PKzip cracker

Has anyone created a PKzip password cracker from an FPGA ?? Google does not find any ...... hamilton
0 comments posted 13yrs
posted by hamilton
0 comments posted 13yrs posted by hamilton

recruit FPGA design engineer in Scotland

The candidate needs to familiar with development of Altera FPGA and Verilog HDL language, It is better if the candidate...
28 comments posted 13yrs
posted by ninauk
28 comments posted 13yrs posted by ninauk

"Decimals" word in binary space

Im looking for an equivalent word for "decimal" in a binary number. The "deci" says it's all about base 10 numbers, but...
12 comments posted 13yrs
posted by mleikvol
12 comments posted 13yrs posted by mleikvol

My Spartan3 video

Hi, I'm not sure, if I posted it allready, but here is my video again : http://www.youtube.com/watch?v=ATiqjJi05IU - Tho...
7 comments posted 13yrs
posted by thorstenkiefer
7 comments posted 13yrs posted by thorstenkiefer

Spartan 3AN prevent readback ?

I am trying to prevent readback of the bit file from a Spartan 3AN. I am using ise 10.1 (need to keep that for a while...
5 comments posted 13yrs
posted by elson
5 comments posted 13yrs posted by elson

xilinx fir compiler

I have used altera DSPBuilder for several multichannel multirate filter designs. I have heard that xilinx fir compiler(...
5 comments posted 13yrs
posted by 3619
5 comments posted 13yrs posted by 3619

spartan 6 ddr2 pinout

I've just run a DDR2 based MIG through place and route and tried the simple= st of pin swaps, which failed. The default...
5 comments posted 13yrs
posted by colin_toogood
5 comments posted 13yrs posted by colin_toogood

how much costs the Artix 7 devices?

Got a newsletter with an advertisment for Xilinx' new Artix 7 devices: http://www.xilinx.com/products/silicon-devices/f...
14 comments posted 14yrs
posted by fb
14 comments posted 14yrs posted by fb

3 to 1 mux with 4 bit inputs

Hi all, I'm learning Verilog. Trying to design a multiplexer: module vector_net_multiplexer_tb; reg [3:0] input1, input...
5 comments posted 14yrs
posted by asp654
5 comments posted 14yrs posted by asp654

manual interconnect changes

Hello, I'm looking for a way to manually change interconnect switch connections. I'm trying to simulate random bit-flip...
1 comments posted 14yrs
posted by billyc59
1 comments posted 14yrs posted by billyc59

Spartan 6 IBERT confusion

If I use the core generator to generate an IBERT for a Spartan 6 and try to= implement the example design the errors I'...
3 comments posted 14yrs
posted by pminmo
3 comments posted 14yrs posted by pminmo

MapLib:978 - LUT6 symbol error during Mapping Stage

Hi, I've recently started to use the Xilinx EDK tools to create a system in whi= ch there are two AXI masters. I made t...
0 comments posted 14yrs
posted by alan.kurusingal
0 comments posted 14yrs posted by alan.kurusingal

Interface Xilinx KC705 to BeagleBone?

I'm playing with the idea of interfacing a BeagleBone (cheap dual ARM Cortex A8 board) to a Xilinx KC705 Kintex develop...
16 comments posted 14yrs
posted by pete_fraser
16 comments posted 14yrs posted by pete_fraser