Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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multi-source errors
Any help is appreciated. I get errors of the following sort: "Multi-source in Unit on signal ; this signal is connec= ted to multiple drivers." The source for the entire unit in question is as...
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11 years ago
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Xilinx CPLD XC95144 for Driving Sigma Delta DAC
hi i would like to drive a Digital to analog converter(AD1933) with a cpld, here is what i'm trying to do: i have a micro controller that generate 25Mbps DAC data but is not capable of driving the DAC...
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11 years ago
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Querying Active-HDL from TCL
This is only approximately the right place to be asking this, but if anyone's going to have an answer, I figure it'll be here. Does anyone know how actually find anything about a design out from a TCL...
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11 years ago
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picoblaze help
hello all, I am new in the field of soft core processor. I want to implement multiple picoblaze on spartan 3E. I had gone through doc available on xilinx website. All demo available on web is working...
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11 years ago
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OpenTech the Largest Open Source package for FPGA designers
Hello, I'd like to announce the new release of OpenTech Package 1.9.0, the first a= nd the largest Open source EDA tools and open source hardware designs distr= ibution package. OpenTech is the first...
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11 years ago
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New(?) fast binary counter for FPGAs without carry logic (e.g. Actel) -- Request For Comment
Dear colleagues, I am sending you a proposal of binary counter, designed to minimize logic path length in between flip-flops to one gate (MUX) only, at the expense of not so straightforward binary...
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11 years ago
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Looking for an extremely cheap FPGA board (in quantity, academic use)
Hi all, I'm looking for a sub-$20 FPGA board (including everything needed to actually use it). Requirements: * The device must have reasonable free software that can handle schematic capture and...
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11 years ago
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Verilog file operations
Hi I want to write some data to a file using Verilog. This file will be a JPEG file so the data in the file needs to be the actual data I write. I have tried using $fwrite but the data ends up as...
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11 years ago
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Unconnected Done pin Virtex 6
Hello, I just received my first FPGA board designed for work, and we have an issue regarding configuration of FPGA. The JTAG chain passed all tests, and the programming proccess starts well (iMPACT)...
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11 years ago
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Delay in Verilog for Asics design which is synthesizable
Can any help me for adding a simple delay of 10ns or more in verilog code which is synthesizable for asics design...... As #10ns etc are not synthesizable.. ---------------------------------------...
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11 years ago
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Problem using virtex 4 and virtex 6 ibis models
I am facing some problems while using IBIS models in hyperlynx. I have to analyze a clock signal coming from 60MHz crystal oscillator and going to virtex 4 FPGA with part number (XC4VLX60-11FF1148) at...
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11 years ago
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General Build Question
Here's a sort of a general toss-out. When I'm writing code in C, one of my rules is that I turn on -Wall (and a mess of other warnings) and I won't ship until I've got 0 warnings in the build. I've...
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11 years ago
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Simulating fixed point multiplica​tion using float ing point core v5.0 on Virtex-6 LX75T ISE 13.4
I am prototyping an algorithm using floating point and fixed point precisio= n. I used the floating point core v 5.0 to generate a multiplier for single= precision multiplication and fixed point...
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11 years ago
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Cross-vendor firmware design management environment
Hi We have developed a cross-vendor firmware design management environment in = our team. It integrates and sync's with many design environments (Sigasi, M= entor Graphics HDL Author etc) and takes...
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11 years ago
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fractional radix agnostic calculator tool?
Im looking for a desktop (win) traditional freeware caclulator that can also convert and handle fractional numbers across different radixes. The builtin winxp and win7 tools are great, but have no...
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11 years ago
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