Field-Programmable Gate Arrays

Querying Active-HDL from TCL

This is only approximately the right place to be asking this, but if anyone's going to have an answer, I figure it'll b...

1 comments posted 13yrs

posted by rgaddi

1 comments posted 13yrs posted by rgaddi

picoblaze help

hello all, I am new in the field of soft core processor. I want to implement multiple picoblaze on spartan 3E. I had go...

4 comments posted 13yrs

posted by rvm.rahul

4 comments posted 13yrs posted by rvm.rahul

OpenTech the Largest Open Source package for FPGA designers

Hello, I'd like to announce the new release of OpenTech Package 1.9.0, the first a= nd the largest Open source EDA tool...

0 comments posted 13yrs

posted by jamil.khatib

0 comments posted 13yrs posted by jamil.khatib

New(?) fast binary counter for FPGAs without carry logic (e.g. Actel) -- Request For Comment

Dear colleagues, I am sending you a proposal of binary counter, designed to minimize logic path length in between flip-...

25 comments posted 13yrs

posted by hefaistos

25 comments posted 13yrs posted by hefaistos

Looking for an extremely cheap FPGA board (in quantity, academic use)

Hi all, I'm looking for a sub-$20 FPGA board (including everything needed to actually use it). Requirements: * The devi...

26 comments posted 13yrs

posted by brehob

26 comments posted 13yrs posted by brehob

Verilog file operations

Hi I want to write some data to a file using Verilog. This file will be a JPEG file so the data in the file needs to be...

5 comments posted 13yrs

posted by 56

5 comments posted 13yrs posted by 56

Unconnected Done pin Virtex 6

Hello, I just received my first FPGA board designed for work, and we have an issue regarding configuration of FPGA. The...

1 comments posted 13yrs

posted by 3669

1 comments posted 13yrs posted by 3669

Delay in Verilog for Asics design which is synthesizable

Can any help me for adding a simple delay of 10ns or more in verilog code which is synthesizable for asics design.........

6 comments posted 13yrs

posted by 3623

6 comments posted 13yrs posted by 3623

Problem using virtex 4 and virtex 6 ibis models

I am facing some problems while using IBIS models in hyperlynx. I have to analyze a clock signal coming from 60MHz crys...

0 comments posted 13yrs

posted by 3615

0 comments posted 13yrs posted by 3615

General Build Question

Here's a sort of a general toss-out. When I'm writing code in C, one of my rules is that I turn on -Wall (and a mess of...

5 comments posted 13yrs

posted by rgaddi

5 comments posted 13yrs posted by rgaddi

Simulating fixed point multiplica​tion using float ing point core v5.0 on Virtex-6 LX75T ISE 13.4

I am prototyping an algorithm using floating point and fixed point precisio= n. I used the floating point core v 5.0 to...

2 comments posted 13yrs

posted by vivek.menon79

2 comments posted 13yrs posted by vivek.menon79

Cross-vendor firmware design management environment

Hi We have developed a cross-vendor firmware design management environment in = our team. It integrates and sync's with...

0 comments posted 13yrs

posted by naude.jaco

0 comments posted 13yrs posted by naude.jaco

fractional radix agnostic calculator tool?

Im looking for a desktop (win) traditional freeware caclulator that can also convert and handle fractional numbers acro...

0 comments posted 13yrs

posted by mleikvol

0 comments posted 13yrs posted by mleikvol

Altera GX45 to GX95 upgrade

Hi, We designed a board that uses an Arria II GX45 chip. We didn't initially figure to use all its resources, but the c...

0 comments posted 13yrs

posted by jjlarkin

0 comments posted 13yrs posted by jjlarkin

How do you do an incdir in Vivado

How do you set up search paths in Vivado so that it will find `includes files? XST supported incdir (in the form of the...

5 comments posted 13yrs

posted by schvantzkoph

5 comments posted 13yrs posted by schvantzkoph