Latest threads in Field-Programmable Gate Arrays

multi-source errors

Any help is appreciated. I get errors of the following sort: "Multi-source in Unit on signal ; this signal is connec= t...

5 14yrs

smileforthecamerahotshot

5 14yrs smileforthecamerahotshot

Xilinx CPLD XC95144 for Driving Sigma Delta DAC

hi i would like to drive a Digital to analog converter(AD1933) with a cpld, here is what i'm trying to do: i have a mic...

24 14yrs

3224

24 14yrs 3224

Querying Active-HDL from TCL

This is only approximately the right place to be asking this, but if anyone's going to have an answer, I figure it'll b...

1 14yrs

rgaddi

1 14yrs rgaddi

picoblaze help

hello all, I am new in the field of soft core processor. I want to implement multiple picoblaze on spartan 3E. I had go...

4 14yrs

rvm.rahul

4 14yrs rvm.rahul

OpenTech the Largest Open Source package for FPGA designers

Hello, I'd like to announce the new release of OpenTech Package 1.9.0, the first a= nd the largest Open source EDA tool...

0 14yrs

jamil.khatib

0 14yrs jamil.khatib

New(?) fast binary counter for FPGAs without carry logic (e.g. Actel) -- Request For Comment

Dear colleagues, I am sending you a proposal of binary counter, designed to minimize logic path length in between flip-...

25 14yrs

hefaistos

25 14yrs hefaistos

Looking for an extremely cheap FPGA board (in quantity, academic use)

Hi all, I'm looking for a sub-$20 FPGA board (including everything needed to actually use it). Requirements: * The devi...

26 14yrs

brehob

26 14yrs brehob

Verilog file operations

Hi I want to write some data to a file using Verilog. This file will be a JPEG file so the data in the file needs to be...

5 14yrs

56

5 14yrs 56

Unconnected Done pin Virtex 6

Hello, I just received my first FPGA board designed for work, and we have an issue regarding configuration of FPGA. The...

1 14yrs

3669

1 14yrs 3669

Delay in Verilog for Asics design which is synthesizable

Can any help me for adding a simple delay of 10ns or more in verilog code which is synthesizable for asics design.........

6 14yrs

3623

6 14yrs 3623

Problem using virtex 4 and virtex 6 ibis models

I am facing some problems while using IBIS models in hyperlynx. I have to analyze a clock signal coming from 60MHz crys...

0 14yrs

3615

0 14yrs 3615

General Build Question

Here's a sort of a general toss-out. When I'm writing code in C, one of my rules is that I turn on -Wall (and a mess of...

5 14yrs

rgaddi

5 14yrs rgaddi

Simulating fixed point multiplicaâ€‹tion using float ing point core v5.0 on Virtex-6 LX75T ISE 13.4

I am prototyping an algorithm using floating point and fixed point precisio= n. I used the floating point core v 5.0 to...

2 14yrs

vivek.menon79

2 14yrs vivek.menon79

Cross-vendor firmware design management environment

Hi We have developed a cross-vendor firmware design management environment in = our team. It integrates and sync's with...

0 14yrs

naude.jaco

0 14yrs naude.jaco

fractional radix agnostic calculator tool?

Im looking for a desktop (win) traditional freeware caclulator that can also convert and handle fractional numbers acro...

0 14yrs

mleikvol

0 14yrs mleikvol

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