Field-Programmable Gate Arrays

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Altera delivery

We are seeing huge leadtimes on Altera FPGAs, specifically Arria II GX65 and 95. Numbers like 20 weeks and worse. Is th...
18 comments posted 14yrs
posted by jjlarkin
18 comments posted 14yrs posted by jjlarkin

production life of Spartan3A ?

Hello, Anybody have any idea how much longer the Spartan 3A will be in production? I'm hoping a good while, yet, as it...
12 comments posted 14yrs
posted by jmelson
12 comments posted 14yrs posted by jmelson

Periodic reads - Xilinx Virtex6

Hello! I read that the MPMC memory controller sends automaticly (1us period) periodic read request to the DDR3 module t...
0 comments posted 14yrs
posted by 3782
0 comments posted 14yrs posted by 3782

JTAG and Altera Cyclone-IV

Hi, I would like to ask for some input. When this device is in JTAG reset state, how does it drive the outputs, hi-Z, 1...
0 comments posted 14yrs
posted by 3758
0 comments posted 14yrs posted by 3758

tell QuartusII to use registers and not RAM

Hi, I'm run out of M9K resources on a design while logic is less than 15% used... and I have a few components in the de...
5 comments posted 14yrs
posted by cupido
5 comments posted 14yrs posted by cupido

Serial LVDS ADC to spartan6

I have to connect a dual 12-bit ADC with serial LVDS outputs (2-lanes per converter) to a spartan 6 FPGA. It would be i...
2 comments posted 14yrs
posted by theller
2 comments posted 14yrs posted by theller

Phase 15.18 placement optimization

I'm working on a Virtex 5 project containing a 13-stage pipeline clocked at 200 MHz. The data path gets quite wide in t...
1 comments posted 14yrs
posted by ah
1 comments posted 14yrs posted by ah

.do files... why?

Alright, I've got to fess up. I'm lost as to the point of .do files. They seem to suffer through all of Tcl's wacky syn...
4 comments posted 14yrs
posted by rgaddi
4 comments posted 14yrs posted by rgaddi

DIGILENT DESIGN CONTEST 2013

We proudly announce the 9th annual Digilent Design Contest Europe, organize d within the Technical University of Cluj-N...
0 comments posted 14yrs
posted by cristina.dabacan
0 comments posted 14yrs posted by cristina.dabacan

My First CPU but.. one problem

Hello to all, I completed my first CPU in VHDL, an incredibly satisfying feeling! : D I simulated successfully but I di...
15 comments posted 14yrs
posted by anon
15 comments posted 14yrs posted by anon

ise 32b or 64b?

Hi! Using Xilinx flow (command line, ISE 13.4)... 32b version vs 64b (under Linux, 64b OS)... memory usage: || | 32b |...
2 comments posted 14yrs
posted by iiahim
2 comments posted 14yrs posted by iiahim