Hello,
I just received my first FPGA board designed for work, and we have an issue regarding configuration of FPGA.
The JTAG chain passed all tests, and the programming proccess starts well (iMPACT)
The issue is an error in status register at the end of programming is returned by iMPACT. Done signal is not high, and I remember now we missed to connect this pin. Actually, on my board, Done pin is floatting.....
Is there a link between these two thinks?
What is the workaround? hard / soft
Thanks for your help.
frapa
--------------------------------------- Posted through
formatting link