Field-Programmable Gate Arrays - Page 154

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• 02-23-2006
• Checkpointing PPC Smartmodels in ModelSim 6.0b Issues
• • Nju Njoroge
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• 4

• 
• 02-22-2006
• JTAG problem
• • mughat
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• 4

• 
• 02-22-2006
• FPGA to ASIC migrate
• • Jerzy Gbur
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• 3

• 
• 02-22-2006
• Ray Andraka's Book?
• • Stephen Craven
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• 9

• 
• 02-22-2006
• state machine and i2c
• • embyembu
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• 1

• 
• 02-22-2006
• PowerPC based SoC design, getting it working from first attempt
• • Antti
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• 3

• 
• 02-22-2006
• configuring stratix GX Fpga
• • pinku
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• 1

• 
• 02-22-2006
• doubt
• • venkatec
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• 1

• -
• 02-22-2006
• RC1000pp with XCV400
• • Colin F
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• 0

• -
• 02-22-2006
• Virtex-4 Output Primitive
• • Brad Smallridge
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• 0

• 
• 02-22-2006
• Cannot use ML310 DDR
• • king_azman
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• 3

• 
• 02-22-2006
• Layer 2 (MAC) Research Project to Eliminate Routers
• • Perfect Queue
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• 1

• 
• 02-21-2006
• Xilinx ISE 6.3 confusion with CPLD logic results
• • Dave Pollum
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• 2

• 
• 02-21-2006
• How to make Customized IP which connected with Microblaze through FSL access the OPB bus?...
• • fpga
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• 11

• 
• 02-21-2006
• bypass between ilogic and ologic
• • Brannon
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• 1

• 
• 02-21-2006
• Relative placement constraints in Xilinx ISE w/ Verilog
• • nestorj
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• 1

• 
• 02-21-2006
• Virtex2: can I really just leave M1,M2,M3 pins floating?
• • ML
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• 1

• 
• 02-21-2006
• fix: Xilinx USB Platform Cable on linux 2.6
• • Stefan
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• 2

• 
• 02-21-2006
• How to use Gigabit transciever
• • pinku
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• 1

• -
• 02-21-2006
• EDK 8.1 SP1 released, DDR2 support is now included !!
• • Antti
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• 0

• 
• 02-21-2006
• DSP
• • SaHiD
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• 1

• 
• 02-21-2006
• SMSC 91c111 and LwIP
• • Marco T.
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• 2

• 
• 02-21-2006
• Xilinx Spartan 3 SSO guidelines for CP132 package?
• • Andrew FPGA
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• 1

• 
• 02-21-2006
• "par.exe" halted without error (partial configuratio)
• • Pasacco
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• 2

• -
• 02-21-2006
• FPGA work - San Diego area
• • great_headhunter
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• 0

• 
• 02-20-2006
• arctangent again
• • m
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• 3

• 
• 02-20-2006
• EDK -running from external sram
• • me_2003
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• 1

• -
• 02-20-2006
• Any one worked with Digilent Adept(transport) feature??
• • k.sandeep.p
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• 0

• -
• 02-20-2006
• JHDL Application
• • baranwal
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• 0

• -
• 02-20-2006
• SDRAM Reading problem
• • raju_lingala
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• 0

• 
• 02-20-2006
• Xilinx 8.1.02i map failure
• • johnp
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• 2

• 
• 02-20-2006
• Is FPGA code called firmware?   [ 2 3 4 ]
• • Marko
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• 80

• 
• 02-20-2006
• Quartus Tcl interface
• • ernie
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• 1

• 
• 02-20-2006
• Inactive signals are active!!! - Chipscope Pro 7.1i - SP4
• • simon.stockton
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• 3

• -
• 02-20-2006
• PPC LUT inputs/outputs
• • munch
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• 0

• 
• 02-20-2006
• DVI - LVDS controller
• • helix
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• 3

• 
• 02-20-2006
• multiphase data extraction question
• • Sandro
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• 6

• 
• 02-20-2006
• Problem with multple clcok domains
• • Sunny
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• 3

• 
• 02-20-2006
• Parameterized Comparator Verilog Code
• • prasunp
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• 1

• -
• 02-20-2006
• Inferring Adder with Carry In and Cary out
• • Sudhir.Singh
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• 0

• 
• 02-19-2006
• FPGA - software or hardware?   [ 2 3 ]
• • Hub van de Bergh
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• 47

• -
• 02-19-2006
• FPGA Board Competition
• • John Adair
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• 0

• 
• 02-19-2006
• help with VGA timings
• • Jordi
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• 10

• 
• 02-19-2006
• Addressing BRAM in a V2 pro
• • Mich
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• 6

• -
• 02-19-2006
• FPT'06: First Call-for-paper
• • Yod
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• 0

• -
• 02-19-2006
• Did anyone doing research on power electronics control using FPGA?
• • kk
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• 0

• 
• 02-19-2006
• What is the best price you have gotten on for these FPGAs?
• • rickman
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• 6

• 
• 02-19-2006
• MontaVista Linux and Virtex-II & 4
• • Osnet
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• 6

• 
• 02-18-2006
• Xilinx ISE Simulator Arrays
• • Brad Smallridge
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• 1

• -
• 02-18-2006
• Approximate power and area values for a 1-bit SRAM cell.
• • vivekgarg330
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• 0