Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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XC5VLX85-2FFG1153C
Can anyone assist is supplying 50 pieces of a Xilinx XC5VLX85-2FFG1153C? I also need 100 pieces of a EP2S130F1508C3N? I can not wait the factory lead time. Please call Jon E. Hansen (949)864-7745...
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16 years ago
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ModelSim versus Active-HDL....redux
Hello all, I'm evaluating ModelSim versus Active-HDL to determine which one is better in today's marketplace (for VHDL). I found some older threads that seemed to lean towards Active-HDL so I wanted...
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16 years ago
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Virtex5 DCM lower limit
Hi all, I've a problem.. :) I have to divide a 48MHz clock to obtain a clock with differents frequencies : 100KHz, 500KHz, 1 MHz or 2 MHz. First I used flips flops to make a frequency divider, I...
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16 years ago
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FSL version compatability with Microblaze version
Hi All , I have am having problems interfacing my custom IP with uBlaze using FSL. I am using the older version of uBlaze (version 4.00.a) and the FSL bus that I am using is version 2.11.a. Is there a...
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16 years ago
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Unsigned to signed vector.
I have a question about a conversion of an unsigned 10-bit vector to signed 8 bit vector. What is the best : signed_data(7 downto 0)
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16 years ago
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Critical Path analysis
Hi I finally have successfully sythesised my design, unfortunately the critical path seems to be quite long so that i have a low frequency. Can anybody tell me whats the best way to identify the...
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16 years ago
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RC340E board to sell
Hello all, I am selling a one-year old Celoxica RC340 Expert board. This board is from Celoxica, the well-know ESL provider. Key features - Virtex-4 4VLX160-10-4 - Dual Gigabit Ethernet MAC/PHY - 4...
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16 years ago
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FYI. Free Verilog cores from MIT.
Saw this on Slashdot. Quote:- Projects H.264: HD quality H.264 baseline profile decoder. OFDM: OFDM transceiver (transmitter and receiver), highly parameterized to cover 802.11a (WiFi), 802.16 (WiMax)...
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16 years ago
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Downloading codes to FPGA development Board
Hi, I have designed a 3-bit counter in Xilinx ISE Webpack software and am trying to download VHDL codes to Spartan 3A FPGA starter kit. Can anyone tell me how to download my codes to FPGA. I am a...
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16 years ago
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microblaze firmware + UART handshaking blues
Hi, I am currently working on a microblaze v6.00 core on FPGA and am developing an algorithm. This is what I am doing 1) matlab on PC sends data to microblaze (FPGA) via UART. RS232 hardware...
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16 years ago
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loading unisim in modelsim problem while testin xilinx ipcore
Hellow, i try to test xilinx IP core and with modelsim but it give error regarding unisim library # Reading D:/Modeltech_pe_edu_6.3c/tcl/vsim/ # do {testfft.fdo} # ** Warning: (vlib-34) Library...
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16 years ago
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ANN CPLD add-on module for Nintendo DS game console
Hi I have a few (5 at the moment) of NDS CPLD boards manufactured, the preliminary user manual is here from that public google project are also available VHDL examples and C code for this CPLD board...
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16 years ago
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My first verilog/cpld project
Not much compared to the "norm" around here, but... Binary to 7-segment chip
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16 years ago
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multidimensional array
Hi, My basic requirement is to have a set of commands for a block. This has been declared as : TYPE command IS ARRAY (NATURAL range ) OF NATURAL; CONSTANT block1_command :command:= ( --...
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16 years ago
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Question to VHDL code fragment
Hi I came across the following code statement, and here I wonder what does this integer'image attribute with the loc(i) mean? This RLOC specifies where to put the stuff on an Xilinx FPGA, but I really...
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16 years ago
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