ModelSim versus Active-HDL....redux

Hello all,

I'm evaluating ModelSim versus Active-HDL to determine which one is better in today's marketplace (for VHDL). I found some older threads that seemed to lean towards Active-HDL so I wanted to see if that was still the case.

I currently use ModelSim Xilinx Edition but my designs often-times hit XE's limits and get throttled.

Also, does know off-hand the approximate price of the different versions? (ModelSim: Designer/PE/SE, Active-HDL: DE/PE/EE) and any key features that make the more expensive ones worth the cost?

Thanks, John

Reply to
paragon.john
Loading thread data ...

I use ActiveHDL , It was the first program I learned to use and I am not changing it for nothing , though I tried ModelSim. Alfredo

Reply to
Alfreeeeed

There is a big difference between Modelsim PE and SE, including a price difference of something like $12K (the last time I looked, which was awhile ago). Also, another thing to consider is Aldec Riviera, rather than ActiveHDL. This is just a high performance simulator, without all the whole "design environment" that ActiveHDL includes.

Also, while you only mention VHDL, keep in mind that you are likely to want to be able to do mixed language simulations. For example, a lot of good memory models seem to only come in Verilog.

Reply to
Duane Clark

I didn't work with ActiveHDL, but I know that with ActiveHDL you cannot do post place and route simulation. This soft is only for behavioral simulation.

Reply to
nezhate

Wrong. You can do all the types of simulation with the same probes that you can do with ModelSim. You probably shouldn't comment on software that you haven't used before.

---Matthew Hicks

Reply to
Matthew Hicks

Is that because it cannot read SDF files?

Reply to
RCIngham

Well, I will have to admit that it has been several years since I have done post place and route simulation. I really don't see much need for that in FPGA design.

Reply to
Duane Clark

ooo now thats a little scary

Bobsterthelobster

Reply to
bobster.thelobster

Prices is difficult, as e.g. PE is not like PE, you can buy different licenses for PE (VHDL vs Verilog, Floating vs Dongle, ...) and you might get deals when buying more than one SW from same vendor.

For the full range of differences have a look at the Mentor homepage.

For me important:

- Performance optimisations is SE only, Performance reduction should be designer only.

- SE has a lot of features included, that need additional payment for the other simulators

- OS support (PE: Win, SE: win, Solaris, Linux (32 and 64 bit), LE: Linux32 only)

- Tcl/Tk support is SE

bye Thomas

Reply to
Thomas Stanka

I don't know where you got that idea. Active HDL simulates a post route netlist just fine. Perhaps you didn't have the simprims library?

Active HDL can also simulate an edif netlist, and can co-simulate with Matlab as a testbench (something I don't think Modelsim does).

I have both, but I use Active HDL for my day to day work. I use Modelsim pretty much only when I don't have a choice.

Reply to
Ray Andraka

Why? I don't use post PAR simulation unless I have a reason to believe the tools messed something up. I can count on my fingers the number of times I've resorted to post PAR simulation. A functional simulation of the RTL followed by a solid timing analysis is far more likely to uncover any problems in the design than a post PAR simulation is.

Reply to
Ray Andraka

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.