Field-Programmable Gate Arrays

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Virtex5 DCM lower limit

Hi all, I've a problem.. :) I have to divide a 48MHz clock to obtain a clock with differents frequencies : 100KHz, 500K...
8 comments posted 18yrs
posted by michel.talon
8 comments posted 18yrs posted by michel.talon

FSL version compatability with Microblaze version

Hi All , I have am having problems interfacing my custom IP with uBlaze using FSL. I am using the older version of uBla...
0 comments posted 18yrs
posted by niladri1979
0 comments posted 18yrs posted by niladri1979

Unsigned to signed vector.

I have a question about a conversion of an unsigned 10-bit vector to signed 8 bit vector. What is the best : signed_data...
9 comments posted 18yrs
posted by lpaulo07
9 comments posted 18yrs posted by lpaulo07

Critical Path analysis

Hi I finally have successfully sythesised my design, unfortunately the critical path seems to be quite long so that i h...
2 comments posted 18yrs
posted by Clemens12
2 comments posted 18yrs posted by Clemens12

RC340E board to sell

Hello all, I am selling a one-year old Celoxica RC340 Expert board. This board is from Celoxica, the well-know ESL prov...
0 comments posted 18yrs
posted by jean.sebastien.leroy
0 comments posted 18yrs posted by jean.sebastien.leroy

FYI. Free Verilog cores from MIT.

Saw this on Slashdot. http://csg.csail.mit.edu.nyud.net/oshd/index.html Quote:- Projects H.264: HD quality H.264 baseli...
1 comments posted 18yrs
posted by symon_brewer
1 comments posted 18yrs posted by symon_brewer

Downloading codes to FPGA development Board

Hi, I have designed a 3-bit counter in Xilinx ISE Webpack software and am trying to download VHDL codes to Spartan 3A F...
3 comments posted 18yrs
posted by anas_waris
3 comments posted 18yrs posted by anas_waris

microblaze firmware + UART handshaking blues

Hi, I am currently working on a microblaze v6.00 core on FPGA and am developing an algorithm. This is what I am doing 1...
13 comments posted 18yrs
posted by chrisdekoh
13 comments posted 18yrs posted by chrisdekoh

ANN CPLD add-on module for Nintendo DS game console

Hi I have a few (5 at the moment) of NDS CPLD boards manufactured, the preliminary user manual is here http://code.goog...
2 comments posted 18yrs
posted by Antti.Lukats
2 comments posted 18yrs posted by Antti.Lukats

My first verilog/cpld project

Not much compared to the "norm" around here, but... http://www.delorie.com/electronics/bin2seven/
15 comments posted 18yrs
posted by dj
15 comments posted 18yrs posted by dj

multidimensional array

Hi, My basic requirement is to have a set of commands for a block. This has been declared as : TYPE command IS ARRAY (N...
0 comments posted 18yrs
posted by vijayant.rutgers
0 comments posted 18yrs posted by vijayant.rutgers

Question to VHDL code fragment

Hi I came across the following code statement, and here I wonder what does this integer'image attribute with the loc(i)...
1 comments posted 18yrs
posted by Clemens12
1 comments posted 18yrs posted by Clemens12

Timing Constraint not met

Hi I put a timing constraint in the UCF File where i asked for a minimum frequency of 35 MHz (29 ns) but unfortuatenly...
5 comments posted 18yrs
posted by Clemi_12
5 comments posted 18yrs posted by Clemi_12

Problem in assignment of pins in PACE

Hi all, I have recently just generated HDL netlist from System Generator 9.1 and I have began assigning the pins in PAC...
0 comments posted 18yrs
posted by hilo_pupu
0 comments posted 18yrs posted by hilo_pupu