Field-Programmable Gate Arrays

Cyclone flash configuration data

I've implemented a flash programmer for the EPCS1 serial flash, attached to a Cyclone, using the Serial Flash Loader en...

4 comments posted 18yrs

posted by fb

4 comments posted 18yrs posted by fb

signal generation in VHDL on FPGA.... Check my code please

hi, i have writen a pice of code which should impliment a value on the LEDs of my FPGA development board as the signal '...

5 comments posted 18yrs

posted by rossalbi

5 comments posted 18yrs posted by rossalbi

i need fpga board with 10 Gig interface and pcie interface

hi all, for my application i need a fpga board which has PCI express interface and 10 Gig ethernet or fibre channel int...

4 comments posted 18yrs

posted by rabbiaqamar

4 comments posted 18yrs posted by rabbiaqamar

i need ur help

i want information about fpga boards. for my application i required a fpga board with pcie interface and 10 Giga bit /s...

1 comments posted 18yrs

posted by rabbiaqamar

1 comments posted 18yrs posted by rabbiaqamar

Erratic Behavior of Virtex 4 FPGA

Hi all, I am using Virtex 4 FPGA (XC4VFX100) in our application. In this, we find some erratic behaiour of FPGA. Whenev...

3 comments posted 18yrs

posted by vicchemical

3 comments posted 18yrs posted by vicchemical

Virtex-4 input pad failures

Out of a lot of 12 boards we've had two now that have experienced input pad failures (shorts to VCCO). These are LVDCI_...

8 comments posted 18yrs

posted by rob

8 comments posted 18yrs posted by rob

CFP: DTVCS 2008 - Design, Testing and Formal Verification Techniques for Integrated Circuits and Systems

Apologies for any multiple copies received. We would appreciate it if you could distribute the following call for paper...

0 comments posted 18yrs

posted by ss.dtvcs

0 comments posted 18yrs posted by ss.dtvcs

Virtex-5 User Guide "Lite"

If you want to get a feel for what you can do with Virtex-5, click on http://www.pldesignline.com/howto/206503253;jsess...

2 comments posted 18yrs

posted by peter

2 comments posted 18yrs posted by peter

Is a FPGA the solution ?

I would like to know if a FPGA is suited for this application: sound sources localization and separation. The algorithm...

4 comments posted 18yrs

posted by Louis-Charles.Caron

4 comments posted 18yrs posted by Louis-Charles.Caron

OT. Posting with Outlook Express?

Hi All, I just found this, and thought it might be of interest. Seems to work quite well. http://home.in.tum.de/~jain/so...

0 comments posted 18yrs

posted by symon_brewer

0 comments posted 18yrs posted by symon_brewer

State machine outputs and tri-state

[I posted this to comp.lang.vhdl, but maybe you FPGA experts know the answer.] Hi I'm not a VHDL expert, just learning,...

8 comments posted 18yrs

posted by grumpsnothere

8 comments posted 18yrs posted by grumpsnothere

HELP on PLL and DCM

Hi, anyone can tell me the differences between PLL and DCM in Virtex5 in terms of pros and cons? thank you.

2 comments posted 18yrs

posted by adam0818

2 comments posted 18yrs posted by adam0818

Xilinx GTP_DUAL: wizard or code ?

I am using for the first time a Xilinx RocketIO module (I have years of FPGA experience though); normally I prefer to e...

1 comments posted 18yrs

posted by tullio.grassi

1 comments posted 18yrs posted by tullio.grassi

When are FPGAs the right choice?

I've been programming embedded micros for a long time, and have a decent understanding of hardware. I finally ordered a...

14 comments posted 18yrs

posted by snarflemike

14 comments posted 18yrs posted by snarflemike

setup time not met in Quartus

Hi all, I have a source clock 125MHz (ck125), and it has a derived clock 25MHz(ck25). I find that Quartus generates ck2...

5 comments posted 18yrs

posted by cmchang72

5 comments posted 18yrs posted by cmchang72