Hi,
I have designed a 3-bit counter in Xilinx ISE Webpack software and am trying to download VHDL codes to Spartan 3A FPGA starter kit. Can anyone tell me how to download my codes to FPGA. I am a beginner so i would prefer a detailed answer. Thanks
Anas.
You need to use the Xilinx ISE Webpack to convert the VHDL (or Verilog) source into a bitstream file (.bit). Then you use either parallell adapter or usb cable to download the bitstream to the Spartan 3A FPGA starter kit. This can be done with the "Impact" application within Xilinx ISE Webpack.
If you want any more help you should state: Operating system. Graphical or commandline user interface. Transfer hardware, parallell or usb.
Hi, Anas. 1st step, Synthesize the code, double click the synthesize command,
2nd step, assign pins in PACE which is found under user constraints command 3rd step: double click implement design.4th step: double click on config bitstream.
Since the last time I used Spartan Starter kit was quite a while ago, I would suggest that mayb you take about 1/2 an hr to go through the help tab/ tutorial on ISE which gives very detail steps on the process especially the last part which involves downloading the bitstream into the kit using iMPACT. You can skip the simulation parts though in that tutorial.
Of course you might have to prepare yourself for any syntax errors of the sort when you go through all the process I have said just now. Wish you luck..
Regards, Bryan
Hi, This tutorial is a good one to get you started, just do as it says, but replace Device Family, Package and Speed Grade according to your FPGA.
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