Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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RAM and shift register constraints
hi all; I am using HWICAP to configure certain LUTs , and as mentioned in the HWICAP data sheet that "when LUTs are configured in Shift Register Mode or as a RAM. If a LUT is modified or just read...
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15 years ago
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Xilinx tools in Windows or Linux - Suggestions
Friends, I have been using the Xilinx tools ISE, EDK in Windows environment. But now planning to use Linux PC for running ISE and EDK. I am curious, which platform (Windows or Linux) is good for...
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15 years ago
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Signal forwarding between FPGAs
Hello Very easy question, but I just wanna make sure that I have done it the correct way so that I dont have to look in this simple stuff for errors :) Basically I have two FPGAs (Control & Target...
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15 years ago
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interfacing lcd to spartan3a dsp 1800
We are students who are trying to interface JHD1629a LCD to spartan 3a dsp 1800 board. In the board the are two slots of EXP connectors. We are confused how to join connect LCD with EXP connector...
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15 years ago
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Beginner : Rotary switch (quad sw)
Spartan 3E starter kit: I tried (like all beginners) to read rotary switch (knob) using FSM with 8 states, 4 for CW and 4 for CCW movements. I did not debounce phased switch inputs. It works fine. But...
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15 years ago
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Writing to memory shared with System Generator
Hi. I'm trying to write a couple of values to a block of memory that is read by the system generator during hw-co-sim. I Use a Sysgen shared memory block in my design. I write to the shared mem. using...
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15 years ago
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edk peripheral communication
Hi I was wondering if anyone can tell me if using edk, is it possible to create 2 separate peripherals with external ports that can communicate with each other? What i'm trying to design is a...
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15 years ago
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Configuration Management Best Practices
I am currently working on a project that takes the same high level behavioral model and ultimately targets both an Altera and a Xilinx chip. About 95% of the code can by synthesized for either Altera...
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15 years ago
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External memory access
Dear everybody, we have experienced a problem with our boards. We are using an Altera Cyclone device with NIOS II processor interfaced with a static RAM and a FLASH memory. The R/W access time for RAM...
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15 years ago
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PPC440 hangs after first interrupt
Hi! I have the following problem on a Virtex5 system: I use an interrupt controller, that is connected to the PPC interrupt port. The interrupt controller and the PPC interrupt handler are initialized...
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15 years ago
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Cycle-based or Event-based simulation?
How do we decide which simulation should we go with for a project? I understand in general VCS is cycle-based simulator and Modelsim is Event-based simulator. But even in VCS when we compile VHDL...
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15 years ago
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Migrating to 9.2i from 8.2i
Dear All I working on a custom based board where the system is running with xilinx 8.2i and Spartan 3E FPGA. Now we are in process of migrating from version 8.2i to 9.2i. Weare facing problem in...
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15 years ago
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1D or 2D Placement for dynamically partially reconfigurable architecture
Hi All: There are many papers about the 1D or 2D placement. However, the papers are almost for the algorithm discussion. The current method for dynamically partially reconfigurable architectures is...
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15 years ago
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How to include the Xilnet library in an EDK project?
hello.... i use EDK 9.1i, and am trying to use opb ethernet on the XUP Virtex 2 Pro board, with PPC 405... in order to implement tcp-ip communication between the board and a pc (windows xp), i wanted...
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15 years ago
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XAUI - INTERNAL LOOPBACK SETUP - DRP (DYNAMIC RECONFIGURATION PORT)
I am trying to enable an internal loopback in a xaui core (near-end PMA loopback) and would like your suggestions on that. I read about the loopback modes in UG196 and found that the DRP's need to be...
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15 years ago
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