How do we decide which simulation should we go with for a project? I understand in general VCS is cycle-based simulator and Modelsim is Event-based simulator.
But even in VCS when we compile VHDL design there is an option to choose the simulation type "Cycle-based" or "Event-based".
Best regards, Muthu
Money Features that you feel are important.
Depending on how you write your RTL code, an event based simulator can perform nearly as well as a cycle based one. Most good simulators already consolidate processes that share the same sensitivity list to reduce overhead. Clocked processes that share the same clock (and async reset, if applicable) get merged, but combinatorial processes, which almost never share entire sensitivity lists, don't. So if you RTL is almost exclusively clocked processes (with very few combinatorial ones), it is for all practical purposes, a cycle based simulation.
Andy
Andy
Cyclebased is a reduction of resolution with gain of speed. You won't do a event based simulation of booting the OS on a microcontroller unless you have really too time in the design schedule :). But a cycle based simulation gives you no chance of simulating designs with multiple clock domains propperly (every asynchronous input is a new clock domain). And you won't learn anything when doing backannotated simulations cycle based.
bye Thomas
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