Field-Programmable Gate Arrays

Type Casting in verilog

I just wanted to know whether type casting in verilog is sythesizable or not?

1 comments posted 18yrs

posted by amboafridi

1 comments posted 18yrs posted by amboafridi

Translate problem

when i try to translate it, it tells me this ERROR:NgdBuild:753 - "top.ucf" Line 4: Could not find instance(s) 'DCM_SP_...

6 comments posted 18yrs

posted by me75

6 comments posted 18yrs posted by me75

Design of a BFSK transmitter/receiver using Xilinx System Generator

I would like someone to comment my BFSK design as I am a student and not much experienced.

1 comments posted 18yrs

posted by kvoskaki

1 comments posted 18yrs posted by kvoskaki

What is TIEOFF_X0Y31

Hi, I ran into a problem which is related to TIEOFF_X0Y31. I opened FPGA_Editor and see such sites around Xilinx Virtex...

3 comments posted 18yrs

posted by adam0818

3 comments posted 18yrs posted by adam0818

on FRAME_ECC_VIRTEX4 functionality

Hi all, I have two questions: 1.- On the meaning of the syndrome word: Virtex-4 Libraries Guide for HDL Designs says th...

5 comments posted 18yrs

posted by rha_x

5 comments posted 18yrs posted by rha_x

EDK question

Hi everybody, I am using PPC to configure number of LUTs using HWICAP, my question is , Is it possible to generate an i...

3 comments posted 18yrs

posted by fatma.abouelella

3 comments posted 18yrs posted by fatma.abouelella

lwip for FPGA

Hi, I am new to using lwip. I am wondering if you can advice me on the same. I need to transfer data from PC to Microbl...

3 comments posted 18yrs

posted by chrisdekoh

3 comments posted 18yrs posted by chrisdekoh

FIR filter with integer coefficients

Hai, Can i implement FIR filter in FPGA using fixed point number.. I referred various FIR filter implementation in FPGA...

1 comments posted 18yrs

posted by rajeshobli

1 comments posted 18yrs posted by rajeshobli

I-map Websolution...turning possibility into reality...

I-Map Websolutions: web hosting Philippines www.imapweb.com - Web Hosting Provider Today=92s modern world we have lots...

0 comments posted 18yrs

posted by friends2philippines

0 comments posted 18yrs posted by friends2philippines

Quartus-II 8.0 resource-sharing? (why inferred addsub takes 2x LUTs?)

I created a simple Verilog-2001 test-module: `default_nettype none module top #( parameter integer D_W = 16 ) ( input w...

1 comments posted 18yrs

posted by hlao

1 comments posted 18yrs posted by hlao

ANNOUNCE: TimingAnalyzer version beta 0.85

Hello All, A new version beta 0.85 is now available. The following changes and additions have occurred. 1 Quickly add p...

9 comments posted 18yrs

posted by timinganalyzer

9 comments posted 18yrs posted by timinganalyzer

arithmetic problem

Hi, the following code : library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; ... rnext.addr

6 comments posted 18yrs

posted by webmaster

6 comments posted 18yrs posted by webmaster

EDK DMA peripherals?

Hi, I am using an EDK-generated PPC subsystem on a ML403. I wonder if it would be complicated to create a peripheral th...

2 comments posted 18yrs

posted by hachti

2 comments posted 18yrs posted by hachti

Missing the simplest things - Active HDL - Beginners Questions

Guys.. I am *brand new* to Aldec Active HDL. What few cpld/pals that I have done have been with CUPL. I've started usin...

1 comments posted 18yrs

posted by jflan

1 comments posted 18yrs posted by jflan

Still a Beginner: Accumulator has no reset

Xilinx ISE 9.2 and ISE 10.1 I wanted to design a simple correlator which correlates a 15 bit sequence with another sequ...

3 comments posted 18yrs

posted by meralonurlu

3 comments posted 18yrs posted by meralonurlu