I am currently working on a project that takes the same high level behavioral model and ultimately targets both an Altera and a Xilinx chip. About 95% of the code can by synthesized for either Altera or Xilinx. Meaning the bulk of the code can be generic without specifying architecture specific primitives. However, the last 5% is presenting some configuration management issues. For instance, I have to instantiate a DCM for Xilinx and a PLL for Altera. Both primitives have similar high level functionality. Considering this I would like to be able to simply exchange a DCM for a PLL when synthesizing between the two architectures. However there are enough differences in port definitions that this idea is not as easy as it would first seem to be. My question to the community is, does anyone have best practices techniques that address the multiple FPGA target problem? Is there a good way to write your code to encourage multiple FPGA development? Also, is there a good way to construct your directory structure within a code repository?
14 years ago