Field-Programmable Gate Arrays

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Signal forwarding between FPGAs

Hello Very easy question, but I just wanna make sure that I have done it the correct way so that I dont have to look in...
14 comments posted 18yrs
posted by Heinrich
14 comments posted 18yrs posted by Heinrich

interfacing lcd to spartan3a dsp 1800

We are students who are trying to interface JHD1629a LCD to spartan 3a dsp 1800 board. In the board the are two slots o...
0 comments posted 18yrs
posted by sumansrb
0 comments posted 18yrs posted by sumansrb

Beginner : Rotary switch (quad sw)

Spartan 3E starter kit: I tried (like all beginners) to read rotary switch (knob) using FSM with 8 states, 4 for CW and...
4 comments posted 18yrs
posted by meralonurlu
4 comments posted 18yrs posted by meralonurlu

Writing to memory shared with System Generator

Hi. I'm trying to write a couple of values to a block of memory that is read by the system generator during hw-co-sim....
0 comments posted 18yrs
posted by klauspetersen
0 comments posted 18yrs posted by klauspetersen

edk peripheral communication

Hi I was wondering if anyone can tell me if using edk, is it possible to create 2 separate peripherals with external po...
1 comments posted 18yrs
posted by godzillalad
1 comments posted 18yrs posted by godzillalad

Configuration Management Best Practices

I am currently working on a project that takes the same high level behavioral model and ultimately targets both an Alte...
5 comments posted 18yrs
posted by erik.k.anderson
5 comments posted 18yrs posted by erik.k.anderson

External memory access

Dear everybody, we have experienced a problem with our boards. We are using an Altera Cyclone device with NIOS II proce...
0 comments posted 18yrs
posted by alessandro.strazzero
0 comments posted 18yrs posted by alessandro.strazzero

PPC440 hangs after first interrupt

Hi! I have the following problem on a Virtex5 system: I use an interrupt controller, that is connected to the PPC inter...
4 comments posted 18yrs
posted by REMOVEallesCAPITALS
4 comments posted 18yrs posted by REMOVEallesCAPITALS

Cycle-based or Event-based simulation?

How do we decide which simulation should we go with for a project? I understand in general VCS is cycle-based simulator...
3 comments posted 18yrs
posted by muthusnv
3 comments posted 18yrs posted by muthusnv

Migrating to 9.2i from 8.2i

Dear All I working on a custom based board where the system is running with xilinx 8.2i and Spartan 3E FPGA. Now we are...
6 comments posted 18yrs
posted by karthick.kr
6 comments posted 18yrs posted by karthick.kr

Linked Group for FPGAs & CPLDs

Hi, There is a new FPGA Linked in Group. Joining will allow you to find and contact other FPGA, CPLD members on LinkedI...
2 comments posted 18yrs
posted by vikashrungta
2 comments posted 18yrs posted by vikashrungta

Xilinx and RAM/ROM monitoring

Hi, I was wondering if a tool exists to monitor the content of a RAM, ROM connected to a Xilinx FPGA. I would like to b...
1 comments posted 18yrs
posted by XSterna
1 comments posted 18yrs posted by XSterna