LDO Noise rejection

What about a 'split' topology? DC path is series, AC path is parallel. The DC to low freq is taken care of in the series regulation, high energy path. The itsy-bitsy AC to HF noise is shaved off with a parallel regulation. You have lot's of voltage in parallel and by syphoning to GND the AC, you could conceivably take this LDO to almost zero voltage across it with some decent noise 'rejection' across the whole band. Not rejection, more absorption.

There'd be some design challenges in splitting the band at the same point, maybe not. But definitely have to look at large transient effects. But overall seems doable.

That's all school-boy stuff... ignores channel-length modulation (the CMOS equivalent of BJT's Early Effect). ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142     Skype: skypeanalog  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.

[...]

Well, the thread is titled LDO Noise rejection.

Presumable you missed the bit further up the thread on 1/f noise.

Mosfet can have 100 times more 1/f nosie, which translates to having to make them 10,000s bigger.

Interesting parts. The threshold accuracy spec of 10 mv is very impressive. Usually, it is not possible to make a reliable current mirror with 0Vt devices. This is because over processes corners and temperature, Vt wants to go way too negative, so control is lost. Even with -10mv max at 25deg, there will still be problems if the current is not large enough to get reasonable Vgst, say 50mv to 100mv

So that's, millions of applications then :-)

Kevin Aylward

- SuperSpice

0.2V:

I don't know if they are all floating gate devices. Apparently you can also adjust the threshold to zero with implantation. Here's a 1994 patent that describes the process:

Google patents shows about 1,070,000 results on Zero Threshold MOSFET. It would probably take some effort to weed out all the spurious hits, but apparently the concept has been around for some time and there are probably many different ways of doing it.

I was thinking of your 1.8V requirement above.

I wonder if the noise from the current mirror is going to be that serious. For example, the NCS2001 works down to 0.9V, which seems to eliminate a bipolar current mirror. Here's the datasheet:

The input stage is a differential N-Channel depletion mode feeding a folded cascade stage and current mirror, presumably cmos. The noise is

100nV/sqrt(Hz), but they don't specify the frequency range.

I wonder if most of the noise is actually from the mosfet input stage, and the input-referred noise from the current mirror would be negligible.

In another example, the MC33201 works down to 1.8V, and the entire op amp is bipolar. The datasheet includes the idealized schematic on page 2:

This op amp has an input noise of 25nV/sqrt(Hz) at 10Hz and 20nV/Sqrt(Hz) at 1KHz.

Again, I wonder if the gain of the input stage wipes out the noise from the current mirror.

Is that "can have", or "will have"? The comparison I show above seems to indicate a ratio of 4, but that is pretty loose since the 10Hz noise is not given for the NCS2001.

This is an interesting topic for me since Rohde seems to feel cmos divider circuits have less phase noise than bipolar.

I'm not following the last sentence clearly, but if control is lost over processes corners and temperature, why not just move the threshold further up so you can keep control. Even if you end up operating at

200mV, it's still better than 0.6V in bipolar.

Actually, I can't think of a single one except in a current mirror:)

It certainly can be.

Ahmmmm....

It all depends on what is trying to be done, and where the current mirror is. The current source in a diff pair, does not contribute much to the noise. The current mirrors in a gilbert cell multiplier do.

For what I have been doing recently, to get the noise performance required would have required having lots of mosfets using at least 100 X the ASIC area of a bipolar version.

A mosfet, of the same area as a bipolar might typically have 1/f noise 100 X, depending on the process and size.

As a fact, one process (0u18 BiCmos) I have used has noise, at L/W = 1u/1u,

300 X that of its 1u X 1u bipolar.

Low noise Mosfet op-amps might well have input transistors occupying half the whole bloody chip. 1/f noise goes with 1/sqrt(A)

Do I need to explain why this would be a major problem when designing a SOC (system on chip) ?

1/f noise of dividers is rarely to never a problem in MOS. Fast edges kill any L.F. noise. Its relatively straightforward to get -170dBc noise floor, with LF noise being > 60dB lower than that of the oscillator in mos. 1/f noise on the control voltage of a VCO is a problem, so is 1/f noise of the oscillator transistor due to up-conversion. LF on the supply of an invertor, is not a problem.

Possibly.

You can't move the Vt, you can increase the Vgst (overdrive voltage, Vgs-Vt) by increasing current, or reducing W/L. Doing so increases the Vsat as Vsat ~ Vgst

For some applications, it may be workable, but it gets to diminishing returns. It can be surprising how designing for all conditions, make simple ideas not really useful in production products.

For 1v8 designs, two diode drops is a problem, hence the beta helper 0Vt mosfet, one diode drop is not so much of a problem. When its gets down to 1v supplies on 45nm, the Vts are designed to be lower, say 250mv, hence easing the design of mirrors.

Kevin Aylward

- SuperSpice

"Works down to", probably means just that. It works, but not very well.

All data sheets are lies, i.e lies of omission. They deliberately try and deceive the user in believing that all specs are met simultaneously.

There is a a "how close to the rails" output spec. There are also specs for gain, phase and psrr. Note that there are no details as to what output voltage this later data was taken at. You can bet your boots its at mid output. Anywhere near 100mv of the rail and everything collapses.

For example, note the distortion graphs on +/-0.5V, Vout is only 0.4 pk-pk, i.e. (0.5V - 0.4/2) = 300mV from the rails!

They don't even dare to show graphs for the claimed +/- 0.45V

For a supply current of 1/2 ma, 100nV/sqrthz is dreadful. A decent bipolar design should be able to archive < 5 nv sqrthz, ignoring the fact a bipolar amp aint going to work 0.9V supply!

Kevin Aylward

- SuperSpice

Precisely where you should shove your ill informed drivel.

Well 35 years ago the magical LM10 came close. Would run on 0.9V at rather above room temp and 1.2V across whole temp range. Can't say what its noise was but surely better than MOS.

piglet

On the S.E.D/Schematics Page of my website...

LDO with +1V output ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142     Skype: skypeanalog  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.

On Sat, 11 Oct 2014 18:20:32 +0100, Pomegranate Bastard Gave us:

The word for today is "slew rate".

Or why else could there be a limitation on trying to retain 5 volt logic swings?

Your mother ill informed you, boy. Your mother illegitimately formed you, boy. Your father should hang for that heinous crime.

Anything you say is ill-egit non-information.

IIRC you DID use a word "clamp", did you not? Such description was incorrect.

Your statement today, "slew rate" IS correct. (As well as power advantages at lower swings.) ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142     Skype: skypeanalog  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.

Precisely.

On Sun, 12 Oct 2014 08:28:21 -0700, Jim Thompson Gave us:

That wasn't me. (I may have, but I don't think so)

Oh, I see. No, not electrical clamping. A clamping down of the maximum speed one can go, and slew rate is the reason. Clamp == hinder, place a ceiling upon, etc.

The best place to be right now seems to be 1.8V "core" with 3.3V I/O, but there are people playing around at 0.9V core. ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142     Skype: skypeanalog  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.

"Best place"? How so? I see plenty of 1.2V cores and 1.8V I/O. The processor I worked on ten years ago was 1.1V I/O and they were trying for .9V (at 100A, it made a difference ;-).